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Run-time Cache Configuration for the LEON-3 Embedded Processor

Published: 31 August 2015 Publication History

Abstract

Cache parameters such as size and associativity are fixed at manufacturing time which are often not tuned for the specific characteristics of each application code. The net result is excessive energy consumption and lower performance. This paper explores the benefits of the use of a reconfigurable data cache in terms of capacity and associativity in a LEON-3 embedded system. We present real energy and execution time results for a set of graph-based and numerical algorithms. For a combined application of these algorithms, the results reveal an aggregate energy savings of 7% and a execution time penalty of just 1% over the best fixed-associativity cache architecture with the same capacity. We further explore the performance of a dynamic cache way shutdown adaptive algorithm and evaluate its performance and energy benefits in the context of the SLAM-EKF position estimation robotics algorithm.

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Cited By

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  • (2022)Evaluating a Machine Learning-based Approach for Cache Configuration2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)10.1109/LASCAS53948.2022.9789040(1-4)Online publication date: 1-Mar-2022
  • (2019)Energy Prediction for Cache Tuning in Embedded Systems2019 IEEE 37th International Conference on Computer Design (ICCD)10.1109/ICCD46524.2019.00091(630-637)Online publication date: Nov-2019
  • (2018)Near Threshold Last Level Cache for Energy Efficient Embedded Applications2018 Ninth International Green and Sustainable Computing Conference (IGSC)10.1109/IGCC.2018.8752134(1-6)Online publication date: Oct-2018
  • Show More Cited By

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Published In

cover image ACM Conferences
SBCCI '15: Proceedings of the 28th Symposium on Integrated Circuits and Systems Design
August 2015
279 pages
ISBN:9781450337632
DOI:10.1145/2800986
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 31 August 2015

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Author Tags

  1. Dynamic cache-way shutdown
  2. FPGA
  3. LEON-3

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  • Research-article
  • Research
  • Refereed limited

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SBCCI '15
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SBCCI '15: 28th Symposium on Integrated Circuits and Systems Design
August 31 - September 4, 2015
Salvador, Brazil

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SBCCI '15 Paper Acceptance Rate 43 of 98 submissions, 44%;
Overall Acceptance Rate 133 of 347 submissions, 38%

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Cited By

View all
  • (2022)Evaluating a Machine Learning-based Approach for Cache Configuration2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS)10.1109/LASCAS53948.2022.9789040(1-4)Online publication date: 1-Mar-2022
  • (2019)Energy Prediction for Cache Tuning in Embedded Systems2019 IEEE 37th International Conference on Computer Design (ICCD)10.1109/ICCD46524.2019.00091(630-637)Online publication date: Nov-2019
  • (2018)Near Threshold Last Level Cache for Energy Efficient Embedded Applications2018 Ninth International Green and Sustainable Computing Conference (IGSC)10.1109/IGCC.2018.8752134(1-6)Online publication date: Oct-2018
  • (2018)Runtime Adaptive Cache for the LEON3 ProcessorApplied Reconfigurable Computing. Architectures, Tools, and Applications10.1007/978-3-319-78890-6_28(343-354)Online publication date: 8-Apr-2018
  • (2016)Design space exploration of cache memory — A survey2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT)10.1109/ICEEOT.2016.7755102(2294-2297)Online publication date: Mar-2016

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