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Duarte Lopes de Oliveira
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2020 – today
- 2023
- [c30]Duarte Lopes de Oliveira, Marcus H. Victor
, Luiz C. Moreira, Felipe F. Nascimento:
Design of Quasi Delay Insensitive Combinational Circuits Based on Optimized DIMS. LASCAS 2023: 1-4 - 2022
- [c29]Gabriel C. Duarte, Duarte Lopes de Oliveira, Gracieth Cavalcanti Batista:
Design of Asynchronous Pipelines with QDI Template Using Commercial FPGA. LASCAS 2022: 1-4 - [c28]Orlando Verducci Jr., Duarte Lopes de Oliveira, Gracieth Cavalcanti Batista:
Fault-Tolerant Finite State Machine Quasi Delay Insensitive in Commercial FPGA Devices. LASCAS 2022: 1-4 - 2021
- [j7]Orlando Verducci Jr.
A novel approach for the design of low-power pipelined synchronous systems operating in double-edge of the clock. Microelectron. J. 107: 104947 (2021) - [c27]Gracieth Cavalcanti Batista, Duarte Lopes de Oliveira, Osamu Saotome:
New Low-Power Architectures of Support Vector Machine Classifier for Speech Recognition System. LASCAS 2021: 1-4 - [c26]Duarte Lopes de Oliveira, Gabriel C. Duarte, Gracieth Cavalcanti Batista:
A New QDI Asynchronous Pipeline with Two-Phase Delay-Insensitive Global Communication. LASCAS 2021: 1-4 - [c25]Orlando Verducci Jr., Duarte Lopes de Oliveira, Robson L. Moreno:
Fault-Tolerant Quasi Delay Insensitive Combinational Circuits in Commercial FPGA Devices. LATS 2021: 1-6 - 2020
- [j6]Gracieth Cavalcanti Batista, Duarte Lopes de Oliveira, Osamu Saotome, Washington Luis Santos Silva:
A low-power asynchronous hardware implementation of a novel SVM classifier, with an application in a speech recognition system. Microelectron. J. 105: 104907 (2020) - [c24]Duarte Lopes de Oliveira, Gabriel C. Duarte, Gracieth Cavalcanti Batista, Diego A. Silva, Leonardo Romano:
Synthesis of Asynchronous State Machines from Synchronous Specifications. LASCAS 2020: 1-4 - [c23]Duarte Lopes de Oliveira, Gabriel C. Duarte, Nicolly N. M. Cardoso, Gracieth Cavalcanti Batista:
Implementation of Asynchronous Pipelines with QDI Template onto FPGAs Using Commercial Tools. SBCCI 2020: 1-5
2010 – 2019
- 2019
- [j5]Gracieth Cavalcanti Batista
Automatic speech patterns recognition of commands using SVM and PSO. Multim. Tools Appl. 78(22): 31709-31731 (2019) - [c22]Tiago S. Curtinhas, Duarte Lopes de Oliveira, Gracieth Cavalcanti Batista, Vitor L. V. Torres, Leonardo Romano:
A State Assignment Method for Extended Burst-Mode gC Finite State Machines Based on Genetic Algorithm. LASCAS 2019: 153-156 - [c21]Duarte Lopes de Oliveira, Orlando Verducci Jr., Vitor L. V. Torres, Gracieth Cavalcanti Batista, Robson L. Moreno
An Implementation of Extended Burst-Mode Specifications as Quasi Delay Insensitive State Machines. LASCAS 2019: 177-180 - [c20]Higor A. Delsoto, Duarte Lopes de Oliveira, Gracieth Cavalcanti Batista, Diego A. Silva, Leonardo Romano:
A Tools Flow for Synthesis of Asynchronous Control Circuits from Extended STG Specifications. LASCAS 2019: 225-228 - [c19]Diego A. Silva, Orlando Verducci Jr., Duarte Lopes de Oliveira:
Implementation of DES Algorithm in New Non-Synchronous Architecture Aiming DPA Robustness. VLSI-SoC 2019: 228-229 - 2018
- [j4]Gabriel Antonio Fanelli de Souza
A novel fully-programmable analog fuzzifier architecture for interval type-2 fuzzy controllers using current steering mirrors. J. Intell. Fuzzy Syst. 34(1): 203-212 (2018) - [c18]Higor A. Delsoto, Duarte Lopes de Oliveira, Lucas Moura Santana, Lester de Abreu Faria:
A design flow of asynchronous burst-mode circuits without fundamental-mode timing assumption. LASCAS 2018: 1-4 - [c17]Duarte Lopes de Oliveira, Tiago S. Curtinhas, Lucas Moura Santana, Lester de Abreu Faria:
A novel state assignment method for XBM AFSMs without the essential hazard assumption. LASCAS 2018: 1-4 - [c16]Duarte Lopes de Oliveira, Kledermon Garcia, Lucas Moura Santana, Lester de Abreu Faria:
FPGA implementation of high-performance asynchronous pipelines with robust control. LASCAS 2018: 1-4 - [c15]Felipe Mendes, Tiago S. Curtinhas, Duarte Lopes de Oliveira, Higor A. Delsoto, Lester de Abreu Faria:
A Novel Tool for Synthesis by Direct Mapping of Asynchronous Circuits from Extended STG Specifications. VLSID 2018: 451-452 - 2017
- [j3]Felipe Tuyama De Faria Barbosa, Duarte Lopes de Oliveira, Tiago S. Curtinhas, Lester de Abreu Faria
Implementation of Locally-Clocked XBM State Machines on FPGAs Using Synchronous CAD Tools. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(5): 1064-1074 (2017) - 2016
- [c14]Duarte Lopes de Oliveira, Felipe Tuyama De Faria Barbosa, Tiago S. Curtinhas, Lester de Abreu Faria, Jocemar F. Sousa:
A design flow for locally-clocked XBM asynchronous state machines using synchronous CAD tools. LASCAS 2016: 251-254 - [c13]Kledermon Garcia, Duarte Lopes de Oliveira, Roberto d'Amore
FPGA implementation of optimized XBM specifications by transformation for AFSMs. ReConFig 2016: 1-6 - [c12]Eduardo Lussari, Duarte Lopes de Oliveira, Lester de Abreu Faria, Orlando Verducci Jr.:
Software-Defined Radio design based on GALS architecture for FPGAs. SBCCI 2016: 1-6 - 2015
- [c11]Duarte Lopes de Oliveira, Tiago S. Curtinhas, Lester de Abreu Faria, Leonardo Romano:
A novel asynchronous interface with pausible clock for partitioned synchronous modules. LASCAS 2015: 1-4 - [c10]Tiago S. Curtinhas, Tassio Cortes Cavalcante
Minimization and Encoding of High Performance Asynchronous State Machines Based on Genetic Algorithm. SBCCI 2015: 4:1-4:6 - 2014
- [c9]Tiago S. Curtinhas, Duarte Lopes de Oliveira, Diego Bompean, Lester de Abreu Faria, Leonardo Romano:
SICARELO: A tool for synthesis of locally-clocked extended burst-mode asynchronous Controllers. LASCAS 2014: 1-4 - [c8]Duarte Lopes de Oliveira, Kledermon Garcia, Roberto d'Amore
Using FPGAs to implement asynchronous pipelines. LASCAS 2014: 1-4 - [c7]Tiago S. Curtinhas, Duarte Lopes de Oliveira, Lester de Abreu Faria, Osamu Saotome:
A novel State Assignment method for Extended Burst-Mode FSM design using Genetic Algorithm. SBCCI 2014: 39:1-39:7 - 2013
- [c6]Duarte Lopes de Oliveira, Diego Bompean, Tiago S. Curtinhas, Lester de Abreu Faria:
Design of locally-clocked asynchronous finite state machines using synchronous CAD tools. LASCAS 2013: 1-4 - [c5]Duarte Lopes de Oliveira, Tiago S. Curtinhas, Lester de Abreu Faria, Leonardo Romano:
Design of synchronous pipeline digital systems operating in double-edge of the clock. LASCAS 2013: 1-4 - [c4]Duarte Lopes de Oliveira, Diego Bompean, Lester de Abreu Faria, Joao Luis V. Oliveira:
Design of asynchronous systems on FPGA using direct mapping and synchronous specification. ReConFig 2013: 1-6
2000 – 2009
- 2008
- [j2]Duarte Lopes de Oliveira, Marius Strum, Sandro S. Sato:
Burst-Mode Asynchronous Controllers on FPGA. Int. J. Reconfigurable Comput. 2008: 926851:1-926851:10 (2008) - 2005
- [c3]Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang
Miriã_SI: a tool for the synthesis of speed-independent multi burst-mode controllers. SBCCI 2005: 56-61 - 2003
- [j1]Duarte Lopes de Oliveira, Marius Strum, Jiang Chau Wang
Miriã: a CAD tool to synthesize multi-burst controllers for heterogeneous systems. Microelectron. Reliab. 43(2): 209-215 (2003) - 2001
- [c2]Duarte Lopes de Oliveira, Wagner Chiepa Cunha, Marius Strum, Wang Jiang Chau:
Synthesis of Multi-Burst Controllers as Modified Huffman Machines. SBCCI 2001: 220-225 - 2000
- [c1]Duarte Lopes de Oliveira, Marius Strum, Wang Jiang Chau, Wagner Chiepa Cunha:
Synthesis of High Performance Extended Burst Mode Asynchronous State Machines. SBCCI 2000: 41-46
Coauthor Index
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