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29th SoCC 2016: Seattle, WA, USA
- Karan S. Bhatia, Massimo Alioto, Danella Zhao, Andrew Marshall, Ramalingam Sridhar:
29th IEEE International System-on-Chip Conference, SOCC 2016, Seattle, WA, USA, September 6-9, 2016. IEEE 2016, ISBN 978-1-5090-1367-8 - Jeannette M. Wing, Danella Zhao:
Opening keynote: Crashing drones and hijacked cameras: Cybertrust meets cyberphysical. 1-3 - Edward A. Lee, Danella Zhao:
Plenary I: The Internet of important things. 1-3 - Danielle Griffith, Karan S. Bhatia:
Tutorial 1A: Design challenges for the Internet of Things. 1-2 - Gururaj Shamanna, Sao-Jie Chen:
Tutorial 1B: Transistors: Past, present and future. 1-2 - Malgorzata Chrzanowska-Jeske, Jürgen Becker
:
Tutorial 2A: 3D integration - challenges and advantages. 1-3 - Jacques Christophe Rudell, Danella Zhao:
Tutorial 2B: CMOS integrated system on a chip for neural interface applications. 1-2 - Partha Pande, Jürgen Becker
Tutorial 3A: Bringing cores closer together: The wireless revolution in on-chip communication. 1-2 - Yong Lian, Andrew Marshall:
Tutorial 3B: The design challenges for self-powered wireless wearable ECG sensor SoC. 1-3 - Visvesh Sathe, Andrew Marshall:
Tutorial 4A: Supply voltage noise and mitigation for real world SoCs. 1-3 - Bhibhudatta Sahoo, Vishal Saxena, Karan S. Bhatia:
Tutorial 4B: ADC design - from system architecture to transistor level design. 1-4 - Shu Hokimoto, Tohru Ishihara
Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing. 1-6 - Stefan Leitner, Paul West, Chao Lu, Haibo Wang:
Digital LDO modeling for early design space exploration. 7-12 - Dadian Zhou
A digital-circuit-based evolutionary-computation algorithm for time-interleaved ADC background calibration. 13-17 - Ming Chen, Po-Tsang Huang, Shang-Lin Wu, Wei Hwang, Ching-Te Chuang:
Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application. 18-23 - Zhidong Bai, Dallas Johnson, Ali Azam, Anirban Saha, Wen Yuan
A 12 bit split-array switched capacitor power amplifier in 130nm CMOS. 24-28 - Xiaoying Deng, Yanyan Mo, Xin Lin, Mingcheng Zhu:
Low-jitter all-digital phase-locked loop with novel PFD and high resolution TDC & DCO. 29-34 - Hyosig Won, Katsuhiro Shimazu:
Statistical design attribute identification for FinFET outlier and Silicon-to-SPICE gap. 35-40 - Jose Eduardo Chiarelli Bueno Filho
Intra-chip traffic generation under autoregressive models based on time series obtained by TLM simulation. 41-46 - Nidhi Batra, Shashwat Kaushik, Anil Kumar Gundu, Mohammad S. Hashmi
A method to estimate effectiveness of weak bit test: Comparison of weak pMOS and WL boost based test - 28nm FDSOI implementation. 47-51 - Mingmin Bai, Dan Zhao, Hongyi Wu:
CATBR-Congestion Aware Traffic Bridging Routing among hierarchical networks-on-chip. 52-57 - Yu Huang:
EDT dynamic bandwidth management (DBM) in SoC testing. 58-63 - Yan Dong, Grady Giles, GuoLiang Li, Jeff Rearick, John Schulze, James Wingfield, Tim Wood:
Toward more efficient scan data bandwidth utilization on modern SOCs. 64-68 - Farrokh Ghani Zadegan, Dimitar Nikolov, Erik Larsson
In-field system-health monitoring based on IEEE 1687. 69-74 - Chongyan Gu, Yijun Cui, Neil Hanley, Máire O'Neill:
Novel lightweight FF-APUF design for FPGA. 75-80 - Mihir N. Mody, Niraj Nandan, Hetul Sanghvi:
Efficient VLSI architecture for SAO decoding in 4K Ultra-HD HEVC video codec. 81-84 - Min-Su Kim, Chunghee Kim, Yong-geol Kim, Ah-Reum Kim, Jikyum Kim, Juhyun Kang, Daeseong Lee, Changjun Choi, Ilsuk Suh, Jungyul Pyo, Youngmin Shin, Jae Cheol Son:
Single-ended D flip-flop with implicit scan mux for high performance mobile AP. 91-95 - Yung-Chun Lei, Tung-Hsuan Lin, Juinn-Dar Huang
Multi-objective sample preparation algorithm for microfluidic biochips supporting various mixing models. 96-101 - Yuxiang Huan, Yifan Qin, Yantian You, Li-Rong Zheng, Zhuo Zou:
A multiplication reduction technique with near-zero approximation for embedded learning in IoT devices. 102-107 - Keissy Guerra Perez, Xin Yang, Sandra Scott-Hayward, Sakir Sezer:
Feature study on a programmable network traffic classifier. 108-113 - Sumon Dey, Paul D. Franzon
Design and ASIC acceleration of cortical algorithm for text recognition. 114-119 - Ali H. Hassan
A 200 MS/s 8-bit Time-based Analog-to-Digital Converter with inherit sample and hold. 120-124 - Weiwei Shi, Chiu-sing Choy:
A 0.4V 320Mb/s 28.7µW 1024-bit configurable multiplier for subthreshold SOC encryption. 125-128 - Emeshaw Ashenafi, Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Low voltage Flash memory design based on floating gate SOFFET. 129-132 - Weifu Li, Paul D. Franzon
Hardware implementation of Hierarchical Temporal Memory algorithm. 133-138 - Bapi Kar
An early global routing framework for uniform wire distribution in SoCs. 139-144 - Amin Rezaei, Masoud Daneshtalab
SAMi: Self-aware migration approach for congestion reduction in NoC-based MCSoC. 145-150 - Kehan Zhu, Vishal Saxena, Xinyu Wu:
Modeling and optimization of the bond-wire interface in a Hybrid CMOS-photonic traveling-wave MZM transmitter. 151-156 - Anupjyoti Deka, Mahalingam Nagarajan:
A Jitter Cancellation Circuit for High Speed I/O Interfaces. 157-162 - Taehoon Kim
A CMOS analog front-end for driving a high-speed SAR ADC in low-power ultrasound imaging systems. 163-168 - Mohammad M. Uzzal, Payman Zarkesh-Ha, Paul Szauter, Jeremy S. Edwards:
Behavioral modeling of drain current of an avalanche ISFET near breakdown. 169-173 - Ali H. Hassan
An ultra-low power voltage-to-time converter (VTC) circuit for low power and low speed applications. 178-182 - Gautham S. Harinarayan, Manmohan Rana, Nitin Pant, Manish Bansal, Sarthak Sharma, Nishant Kaundal:
Automated Full Chip SPICE simulations with self-checking assertions for last mile verification & first pass Silicon of mixed signal SoCs. 183-188 - Mohammad M. Uzzal, Payman Zarkesh-Ha, Paul Szauter, Jeremy S. Edwards:
Analytical noise model for avalanche ISFET sensor suitable for Next Generation Sequencing. 189-193 - Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
Rotator-based multiplexer network synthesis for field-data extractors. 194-199 - Abhilash Karnatakam Nagabhushana, Haibo Wang:
A comparator timing assisted SAR ADC technique with reduced conversion cycles. 200-205 - Shady Mohamed Soliman, Baher Magdy, Mohamed A. Abd El-Ghany
Efficient implementation of the AES algorithm for security applications. 206-210 - Filippo Neri, Craig Keogh, Thomas Brauner, Eric De Mey, Christian Schippel:
High-voltage low-power startup backup battery switch using low voltage devices in 28nm CMOS. 211-216 - Sao-Jie Chen, Grace Liu, Hsin-Ping Yang, Cheng-Hao Luo, Wen-Mei W. Hwu:
Design of a power-efficient ARM processor with a timing-error detection and correction mechanism. 217-222 - Stefan Leitner, Haibo Wang, Spyros Tragoudas:
Compressive image sensor technique with sparse measurement matrix. 223-228 - Mohammad A. Ahmed, Sucheta Mohapatra, Malgorzata Chrzanowska-Jeske:
Performance optimization and power efficiency in 3D IC with buffer insertion scheme. 229-234 - Yongshik Moon, Soonhyun Noh, Daedong Park, Chen Luo, Anshumali Shrivastava, Seongsoo Hong, Krishna V. Palem:
CaPSuLe: A camera-based positioning system using learning. 235-240 - Mike Fagan, Jeremy Schlachter, Kazutomo Yoshii, Sven Leyffer
Overcoming the power wall by exploiting inexactness and emerging COTS architectural features: Trading precision for improving application quality. 241-246 - Youchang Kim, Injoon Hong, Seongwook Park, Hoi-Jun Yoo:
Low-power real-time intelligent SoCs for smart machines. 247-252 - Luhao Wang, Tiansong Cui, Shahin Nazarian, Yanzhi Wang, Massoud Pedram:
Standard cell library based layout characterization and power analysis for 10nm gate-all-around (GAA) transistors. 253-258 - Darya Almasi, Houman Homayoun, Hassan Salmani, Hamid Mahmoodi
Comparative analysis of hybrid Magnetic Tunnel Junction and CMOS logic circuits. 259-264 - Sao-Jie Chen, Hsin-Ping Yang, Ding-Jyun Lin, Grace Liu:
Modeling and simulation of quantum-well infrared photodetectors. 265-270 - Motoi Ichihashi, Jia Zeng, Cole Zemke, Irene Lin, Greg Northrop, Ning Jin, Jongwook Kye:
Sensitivity analysis for SoC performance benchmark against interconnect parasitic resistance and capacitance beyond 10-nm FinFET technology. 271-274 - Seong Jae Hyeon, Kwang Sub Yoon, Soo Hun Yang:
A low power fourth order ΣΔ CMOS modulator with subthreshold amplifier. 275-279 - Pulkit Sharma, Mohammad S. Hashmi
A novel design of a Dual Functionality Read-Write driver for SRAM. 280-285 - Moez El-Massry, Moataz M. Medhat, Hassan Mostafa
Novel ultra low voltage mobile compatible RF MEMS switch for reconfigurable microstrip antenna. 286-289 - Prakhar Raj Gupta, G. S. Visweswaran, Gaurav Narang, Anuj Grover
Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework. 290-295 - Ting-Yu Shyu, Bo-Yu Su, Tay-Jyi Lin, Chingwei Yeh, Jinn-Shyan Wang, Tien-Fu Chen:
Variable-length VLIW encoding for code size reduction in embedded processors. 296-299 - Shun-Wen Cheng:
Self-dual diamond-graph CMOS H-bridge logic family. 300-305 - Somayeh Maabi, Farshad Safaei, Amin Rezaei, Masoud Daneshtalab
ERFAN: Efficient reconfigurable fault-tolerant deflection routing algorithm for 3-D Network-on-Chip. 306-311 - Ao Ren, Bo Yuan, Yanzhi Wang:
Design of high-speed low-power polar BP decoder using emerging technologies. 312-316 - Ruizhe Cai, Ao Ren, Yanzhi Wang, Sucheta Soundarajan, Qinru Qiu, Bo Yuan, Paul Bogdan:
A low-computation-complexity, energy-efficient, and high-performance linear program solver using memristor crossbars. 317-322 - Bo Yuan:
Efficient hardware architecture of softmax layer in deep neural network. 323-326 - Saeid Barzegarjalali, Kun Yue, Alice C. Parker:
Noisy neuromorphic circuit modeling Obsessive Compulsive Disorder. 327-332 - Xiang Chen, Kent W. Nixon, Yiran Chen:
Practical power consumption analysis with current smartphones. 333-337 - Shixiong Jiang, Vijayalakshmi Saravanan, Pengzhan Yan, Ramalingam Sridhar:
A fully parallel content addressable memory design using multi-bank structure. 338-343 - Hai Wang, Ming Zhang, Sheldon X.-D. Tan, Chi Zhang, Yuan Yuan, Keheng Huang, Zhenghong Zhang:
New power budgeting and thermal management scheme for multi-core systems in dark silicon. 344-349 - Yi-Hsuan Ting, Chih-Yang Wang, Yu-Sian Chang, Tay-Jyi Lin, Shih-Chieh Chang, Jinn-Shyan Wang:
Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation. 350-355 - Sandip Ray, Jayanta Bhadra:
Security challenges in mobile and IoT systems. 356-361 - Raj Gautam Dutta, Xiaolong Guo, Yier Jin
Quantifying trust in autonomous system under uncertainties. 362-367 - Wen Chen, Jayanta Bhadra:
Striking a balance between SoC security and debug requirements. 368-373
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