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2020 – today
- 2023
- [c87]Yi-Pei Su, Chao-Yen Huang, Sao-Jie Chen:
A Robust Super-Regenerative Receiver with Optimal Detection on BER Level. ISCAS 2023: 1-5 - 2022
- [c86]Chien-Hsiang Lin, Yi-Pei Su, Yean-Ru Chen, Yu-Ting Chou, Sao-Jie Chen:
Empirical Study of Proposed Meltdown Attack Implementation on BOOM v3. MWSCAS 2022: 1-4 - [c85]Hang Chen, Yi-Pei Su, Yean-Ru Chen, Chi-Chieh Chiu, Sao-Jie Chen:
Robustness Analysis of Neural Network Designs for ReLU Family and Batch Normalization. TAAI 2022: 1-6 - 2021
- [j48]Yi-Pei Su
, Chao-Yen Huang, Sao-Jie Chen
A 24-GHz Fully Integrated CMOS Transceiver for FMCW Radar Applications. IEEE J. Solid State Circuits 56(11): 3307-3317 (2021) - [c84]Tung-Liang Lin
An Error Resilient Design Platform for Aggressively Reducing Power, Area and Routing Congestion. ISQED 2021: 172-177 - 2020
- [j47]Tung-Liang Lin
A Platform of Resynthesizing a Clock Architecture Into Power-and-Area Effective Clock Trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2475-2488 (2020) - [c83]Tung-Liang Lin, Sao-Jie Chen:
DVFS Considering Spatial Correlation Timing and Process-Voltage-Temperature Variations. SoCC 2020: 141-146
2010 – 2019
- 2018
- [c82]Shu-Min Liu, Chen-Yu Li, Sao-Jie Chen:
Application of BSS Algorithms for Breast Cancer Detection. DSP 2018: 1-4 - [c81]Shu-Min Liu, Zi-Yuan Lin, Je-Luen Ju, Sao-Jie Chen:
Acceleration of Variant Discovery Tool in GATK. DSP 2018: 1-4 - 2017
- [c80]Bor-Shing Lin
Efficient Mobile Middleware for Seamless Communication of Prehospital Emergency Medicine. ECC 2017: 147-156 - 2016
- [j46]Wen-Chung Tsai, Wei-De Chen, Ying-Cherng Lan, Yu Hen Hu, Sao-Jie Chen
A BiNoC architecture - aware task allocation and communication scheduling scheme. Microprocess. Microsystems 42: 215-226 (2016) - [c79]Gururaj Shamanna, Sao-Jie Chen:
Tutorial 1B: Transistors: Past, present and future. SoCC 2016: 1-2 - [c78]Sao-Jie Chen, Grace Liu, Hsin-Ping Yang, Cheng-Hao Luo, Wen-Mei W. Hwu:
Design of a power-efficient ARM processor with a timing-error detection and correction mechanism. SoCC 2016: 217-222 - [c77]Sao-Jie Chen, Hsin-Ping Yang, Ding-Jyun Lin, Grace Liu:
Modeling and simulation of quantum-well infrared photodetectors. SoCC 2016: 265-270 - 2015
- [j45]Bor-Shing Lin
Temporal and Spatial Denoising of Depth Maps. Sensors 15(8): 18506-18525 (2015) - [c76]Bor-Shing Lin, Wei-Ren Chou, Chu Yu, Po-Hsun Cheng, Po-Jui Tseng, Sao-Jie Chen
An effective spatial-temporal denoising approach for depth images. DSP 2015: 647-651 - [c75]Ming-Lun Lee, Chun Nien, Chieh-Hsiung Kuan
Improved Fourier series expansion methods for electrocardiography analysis. DSP 2015: 652-654 - [c74]Jung-Hong Po, Sao-Jie Chen
Variable code length soft-output decoder of polar codes. DSP 2015: 655-658 - [c73]Hsin-Ping Yang, Meng-Hsuan Ho, Hsiao-Chi Hsieh, Po-Hsun Cheng, Sao-Jie Chen
Hardware implementation of a real-time distributed video decoder. DSP 2015: 659-664 - [c72]Bor-Shing Lin, Huey-Dong Wu
Using Back-Propagation Neural Network for Automatic Wheezing Detection. IIH-MSP 2015: 49-52 - [c71]Hsin-Ping Yang, Hsiao-Chi Hsieh, Sheng-Hsiang Chang, Sao-Jie Chen
An improved distributed video coding with low-complexity motion estimation at encoder. SoCC 2015: 111-114 - [c70]Wen-Chung Tsai, Hsiao-En Lin, Ying-Cherng Lan, Sao-Jie Chen
A novel flow fluidity meter for BiNoC bandwidth resource allocation. SoCC 2015: 281-286 - 2014
- [j44]Yean-Ru Chen, Jia-Jen Yeh, Pao-Ann Hsiung, Sao-Jie Chen
Accelerating Coverage Estimation Through Partial Model Checking. IEEE Trans. Computers 63(7): 1613-1625 (2014) - [c69]Chu Yu, Ho-Sheng Chuang, Bor-Shing Lin, Po-Hsun Cheng, Sao-Jie Chen
Improvement on a block-serial fully-overlapped QC-LDPC decoder for IEEE 802.11n. ICCE 2014: 446-447 - [c68]Wen-Chung Tsai, Deng-Yuan Zheng, Sao-Jie Chen
A prefetching scheme for Automatic Repeat-reQuest fault-tolerant on-chip network. ICMLC 2014: 345-351 - [c67]Yean-Ru Chen, Sao-Jie Chen
Unified Security and Safety Risk Assessment - A Case Study on Nuclear Power Plant. TSA 2014: 22-28 - 2013
- [j43]Wen-Chung Tsai, Deng-Yuan Zheng, Yu Hen Hu, Sao-Jie Chen
A unified link-layer fault-tolerant architecture for network-based many-core embedded systems. J. Syst. Archit. 59(7): 492-504 (2013) - [j42]Wen-Chung Tsai, Kuo-Chih Chu, Yu Hen Hu, Sao-Jie Chen
Non-minimal, turn-model based NoC routing. Microprocess. Microsystems 37(8-B): 899-914 (2013) - [j41]Jui-Chieh Lin, Sao-Jie Chen
Cycle-Efficient LFSR Implementation on Word-Based Microarchitecture. IEEE Trans. Computers 62(4): 832-838 (2013) - [c66]Wen-Chung Tsai, Yi-Yao Weng, Chun-Jen Wei, Sao-Jie Chen, Yu Hen Hu:
3D Bidirectional-Channel Routing Algorithm for Network-Based Many-Core Embedded Systems. EMC/HumanCom 2013: 301-309 - [c65]Chu Yu, Yu-Shan Su, Bor-Shing Lin, Po-Hsun Cheng, Sao-Jie Chen
A dual-code-rate memoryless Viterbi decoder for wireless communication systems. ICCE 2013: 578-579 - [c64]Yu-Shan Su, Chu Yu, Bor-Shing Lin, Po-Hsun Cheng, Sao-Jie Chen
Design of a (255, 239) Reed-Solomon decoder using a simplified step-by-step algorithm. ISCE 2013: 247-248 - [c63]Yean-Ru Chen, Zi-Rong Wangt, Pao-Ann Hsiung, Sao-Jie Chen
Backward probing deadlock detection for networks-on-chip. NOCS 2013: 1-2 - [c62]Chun-Jen Wei, Shu-Min Liu, Sao-Jie Chen, Yu Hen Hu:
Optimal fixedl-point fast fourier transform. SiPS 2013: 377-382 - [c61]Chun-Jen Wei, Yi-Yao Weng, Wen-Chung Tsai, Sao-Jie Chen
Novel time-multiplexing bidirectional on-chip network. SoCC 2013: 210-215 - 2012
- [j40]Wen-Chung Tsai, Ying-Cherng Lan, Yu Hen Hu, Sao-Jie Chen
Networks on Chips: Structure and Design Methodologies. J. Electr. Comput. Eng. 2012: 509465:1-509465:15 (2012) - [j39]Sao-Jie Chen
Networks-on-Chip: Architectures, Design Methodologies, and Case Studies. J. Electr. Comput. Eng. 2012: 634930:1 (2012) - [j38]Tsan-Nan Chien, Sung-Huai Hsieh
Usability Evaluation of Mobile Medical Treatment Carts: Another Explanation by Information Engineers. J. Medical Syst. 36(3): 1327-1334 (2012) - [j37]Wen-Chung Tsai, Kuo-Chih Chu, Yu Hen Hu, Sao-Jie Chen
A scalable and fault-tolerant network routing scheme for many-core and multi-chip systems. J. Parallel Distributed Comput. 72(11): 1433-1441 (2012) - [j36]Guan-Ju Peng
AND-OR tree-based mode selection for video coding. Signal Image Video Process. 6(2): 259-271 (2012) - [j35]Chun-Jen Wei, Howard Chen, Sao-Jie Chen
Design and Implementation of Block-Based Partitioning for Parallel Flip-Chip Power-Grid Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(3): 370-379 (2012) - [j34]Chu Yu, Chen-Hen Sung, Chien-Hung Kuo, Mao-Hsu Yen, Sao-Jie Chen
Design and implementation of a low-power OFDM receiver for wireless communications. IEEE Trans. Consumer Electron. 58(3): 739-745 (2012) - [j33]Guan-Ju Peng
Interlayer Bit Allocation for Scalable Video Coding. IEEE Trans. Image Process. 21(5): 2592-2606 (2012) - [c60]Po-Hsun Cheng, Shun-Hsiang Hu, Yu-Pao Lin, Hsiao-Chi Hsieh, Bor-Shing Lin, Chu Yu, Sao-Jie Chen
A Ubiquitous Scheme for a One-to-Many Switching Tunnel for Healthcare Utilization. CICSyN 2012: 389-392 - [c59]Hung-Lin Chao, Yean-Ru Chen, Sheng-Ya Tong, Pao-Ann Hsiung, Sao-Jie Chen:
Congestion-aware scheduling for NoC-based reconfigurable systems. DATE 2012: 1561-1566 - [c58]Jui-Chieh Lin, Sao-Jie Chen
Cycle-efficient lineary feedback shift register implementation on word-based micro-architecture. ICASSP 2012: 1613-1616 - [c57]Chu Yu, Chien-Hung Kuo, Chen-Hen Sung, Mao-Hsu Yen, Sao-Jie Chen
Design of a low-power OFDM baseband receiver for wireless communications. ICCE 2012: 548-549 - [c56]Guan-Ju Peng
Optimal Bit-allocation for Wavelet-based Scalable Video Coding. ICME 2012: 663-668 - 2011
- [j32]Ying-Cherng Lan, Yueh-Chi Lin, Shih-Hsin Lo, Yu Hen Hu, Sao-Jie Chen
A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 427-440 (2011) - [j31]Chu Yu, Mao-Hsu Yen, Pao-Ann Hsiung, Sao-Jie Chen
A low-power 64-point pipeline FFT/IFFT processor for OFDM applications. IEEE Trans. Consumer Electron. 57(1): 40 (2011) - [c55]Wen-Chung Tsai, Deng-Yuan Zheng, Sao-Jie Chen, Yu Hen Hu:
A fault-tolerant NoC scheme using bidirectional channel. DAC 2011: 918-923 - [c54]Guan-Ju Peng, Wen-Liang Hwang, Sao-Jie Chen:
Rate-allocation for spatially scalable video coding. ISPA 2011: 367-372 - [c53]Yi-Pei Su, Wei-Yi Hu, Jia-Wei Lin, Yun-Chung Chen, Sakir Sezer, Sao-Jie Chen
Low power Gm-boosted differential Colpitts VCO. SoCC 2011: 247-250 - 2010
- [j30]Mei-Ju Su, Jia-Wei Lin, Yen-Ting Chen, Yaw-Jen Lin, Yu-Huei Su, Sao-Jie Chen
Web 2.0 Teacher Community in a National Health E-learning Network. Int. J. E Health Medical Commun. 1(2): 51-60 (2010) - [j29]Yang-Shan Tong, Sao-Jie Chen
An Automatic Optical Simulation-Based Lithography Hotspot Fix Flow for Post-Route Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 671-684 (2010) - [j28]Ya-Nan Wen, Guang-Huei Lin, Sao-Jie Chen
Optimal Multiple-Bit Huffman Decoding. IEEE Trans. Circuits Syst. Video Technol. 20(5): 621-631 (2010) - [c52]Jui-Chieh Lin, Ming-Jung Fan-Chiang, Minja Hsieh, Song-Yen Mao, Sao-Jie Chen
Cycle efficient scrambler implementation for software defined radio. ICASSP 2010: 1586-1589 - [c51]Shih-Hsin Lo, Ying-Cherng Lan, Hsin-Hsien Yeh, Wen-Chung Tsai, Yu Hen Hu, Sao-Jie Chen
QoS aware BiNoC architecture. IPDPS 2010: 1-10 - [c50]Jui-Chieh Lin, Minja Hsieh, Ming-Jung Fan-Chiang, Song-Yen Mao, Chu Yu, Sao-Jie Chen
Perfect shuffling for cycle efficient puncturer and interleaver for software defined radio. ISCAS 2010: 3965-3968 - [c49]Sao-Jie Chen
ARAL-CR: An adaptive reasoning and learning cognitive radio platform. ICSAMOS 2010: 324-331 - [c48]Wen-Chung Tsai, Ying-Cherng Lan, Sao-Jie Chen
DyML: Dynamic Multi-Level flow control for Networks on Chip. SoCC 2010: 429-434 - [c47]Wen-Chung Tsai, Kuo-Chih Chu, Sao-Jie Chen
TM-FAR: Turn-Model based Fully Adaptive Routing for Networks on Chip. VLSI-SoC 2010: 19-24
2000 – 2009
- 2009
- [j27]Po-Hsun Cheng, Sao-Jie Chen
Evolution and Integration of Medical Laboratory Information System in an Asia National Medical Center. IEICE Trans. Commun. 92-B(2): 379-386 (2009) - [j26]Chin-Fu Ku, Yu-Fang Zheng, Sao-Jie Chen, Jan-Ming Ho:
USVoD: A Large Scale Video-on-Demand System Based on Uniform Sampling Cache Mechanism. J. Inf. Sci. Eng. 25(1): 219-233 (2009) - [c46]Yean-Ru Chen, To-Yu Chen, Pao-Ann Hsiung, Sao-Jie Chen, Yu Hen Hu:
Compositional Automata Reduction with Non-critical Path Slicing. FCS 2009: 133-138 - [c45]Fong-Ming Shyu, Po-Hsun Cheng, Sao-Jie Chen
Using XML for VLSI Physical Design Automation. ICA3PP 2009: 821-831 - [c44]Jia-Wei Lin, Da-Tong Yen, Wei-Yi Hu, Chu Yu, Mao-Hsu Yen, Pao-Ann Hsiung, Sao-Jie Chen
A 900 MHz to 5.2 GHz Dual-loop Feedback Multi-band LNA. ISCAS 2009: 1024-1027 - [c43]Ying-Pei Chen, Tsan-Nan Chien, Po-Hsun Cheng, Sao-Jie Chen
An Agile and Low Cost FPGA Implementation of MPEG-2 TS Remultiplexer for CATV Head-End Equipment. ISPAN 2009: 722-726 - [c42]Yang-Shan Tong, Chia-Wei Lin, Sao-Jie Chen
An automatic optical-simulation-based lithography hotspot fix flow for post-route optimization. ISPD 2009: 115-122 - [c41]Ying-Cherng Lan, Michael C. Chen, Wei-De Chen, Sao-Jie Chen
Performance-energy tradeoffs in reliable NoCs. ISQED 2009: 141-146 - [c40]Ying-Cherng Lan, Shih-Hsin Lo, Yueh-Chi Lin, Yu Hen Hu, Sao-Jie Chen
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel. NOCS 2009: 266-275 - [c39]Jui-Chieh Lin, Chu Yu, Mao-Hsu Yen, Pao-Ann Hsiung, Sao-Jie Chen
Parallel implementation of convolution encoder for software defined radio on DSP architecture. ICSAMOS 2009: 180-186 - [c38]Jui-Chieh Lin, Minja Hsieh, Ming-Jung Fan-Chiang, Chu Yu, Sao-Jie Chen
An instruction set architecture independent design method for embedded OFDM-based software defined transmitter. SoCC 2009: 207-210 - 2008
- [j25]Po-Hsun Cheng, Sao-Jie Chen
A Collaborative Knowledge Management Process for Implementing Healthcare Enterprise Information Systems. IEICE Trans. Inf. Syst. 91-D(6): 1664-1672 (2008) - [c37]Ying-Cherng Lan, Michael C. Chen, Alan P. Su, Yu Hen Hu, Sao-Jie Chen
Flow Maximization for NoC Routing Algorithms. ISVLSI 2008: 335-340 - [c36]Ying-Cherng Lan, Michael C. Chen, Alan P. Su, Yu Hen Hu, Sao-Jie Chen
Fluidity concept for NoC: A congestion avoidance and relief routing scheme. SoCC 2008: 65-70 - 2007
- [b1]Tsung-Yi Ho
Full-Chip Nanometer Routing Techniques. Analog Circuits and Signal Processing, Springer 2007, ISBN 978-1-4020-6194-3, pp. I-XI, 1-102 - [c35]Yaw-Jen Lin, Mei-Ju Su, Sao-Jie Chen
A Study of Ubiquitous Monitor with RFID in an Elderly Nursing Home. MUE 2007: 336-340 - [c34]Yean-Ru Chen, Pao-Ann Hsiung, Sao-Jie Chen:
Modeling and Automatic Failure Analysis of Safety-Critical Systems Using Extended Safecharts. SAFECOMP 2007: 451-464 - [c33]Guang-Huei Lin, Ya-Nan Wen, Xiao-Long Wu, Sao-Jie Chen
Design of a SIMD multimedia SoC platform. SoCC 2007: 51-54 - [c32]Chun-Jen Wei, Guang-Huei Lin, Ya-Nan Wen, Sao-Jie Chen
Symbolic verification and error prediction methodology. SoCC 2007: 201-204 - 2006
- [j24]Jyh Perng Fang, Yang-Shan Tong, Sao-Jie Chen
An Enhanced BSA for Floorplanning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(2): 528-534 (2006) - [j23]Tsung-Yi Ho
Multilevel routing with jumper insertion for antenna avoidance. Integr. 39(4): 420-432 (2006) - [j22]Bor-Shyh Lin
RTWPMS: A Real-Time Wireless Physiological Monitoring System. IEEE Trans. Inf. Technol. Biomed. 10(4): 647-656 (2006) - [c31]Guang-Huei Lin, Sao-Jie Chen
Memory Access Optimization of Motion Estimation Algorithms on a Native SIMD PLX Processor. APCCAS 2006: 566-569 - [c30]Chia-Hsiung Chen, Sao-Jie Chen
Edge Detection on the Bayer Pattern. APCCAS 2006: 1132-1135 - [c29]Ya-Nan Wen, Guan-Lin Wu, Sao-Jie Chen
Multiple-Symbol Parallel CAVLC Decoder for H.264/AVC. APCCAS 2006: 1240-1243 - [c28]Pei-Yung Hsiao, Chia-Hsiung Chen, Shin-Shian Chou, Le-Tien Li, Sao-Jie Chen:
A parameterizable digital-approximated 2D Gaussian smoothing filter for edge detection in noisy image. ISCAS 2006 - [c27]Ya-Nan Wen, Sao-Jie Chen
Optimal Multiple-Bit Huffman Decoding. SoCC 2006: 79-82 - 2005
- [j21]Yong-Hsiang Hsieh, Wei-Yi Hu, Wen-Kai Li, Shin-Ming Lin, Chao-Liang Chen, David J. Chen, Sao-Jie Chen:
A 6.25 mm2 2.4 GHz CMOS 802.11b Transceiver. IEICE Trans. Electron. 88-C(8): 1716-1722 (2005) - [j20]Yong-Hsiang Hsieh, Wei-Yi Hu, Shin-Ming Lin, Chao-Liang Chen, Wen-Kai Li, Sao-Jie Chen
An auto-I/Q calibrated CMOS transceiver for 802.11g. IEEE J. Solid State Circuits 40(11): 2187-2192 (2005) - [j19]Tsung-Yi Ho
Crosstalk- and performance-driven multilevel full-chip routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6): 869-878 (2005) - [c26]Chin-Fu Ku, Sao-Jie Chen
Improving End-to-End Performance by Active Queue Management. AINA 2005: 337-340 - [c25]Tsung-Yi Ho
Multilevel full-chip routing for the X-based architecture. DAC 2005: 597-602 - 2004
- [j18]Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen
Fast postplacement optimization using functional symmetries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 102-118 (2004) - [c24]Tsung-Yi Ho
Multilevel routing with antenna avoidance. ISPD 2004: 34-40 - [c23]Tsung-Yi Ho
Multilevel routing with jumper insertion for antenna avoidance. SoCC 2004: 63-66 - 2003
- [c22]Tsung-Yi Ho
A Fast Crosstalk- and Performance-Driven Multilevel Routing System. ICCAD 2003: 382-387 - [c21]Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen:
A crosstalk aware two-pin net router. ISCAS (5) 2003: 485-488 - [c20]Jyh Perng Fang, Sao-Jie Chen:
Tile-graph-based power planning. ISCAS (5) 2003: 501-504 - [c19]Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen:
Minimizing coupling jitter by buffer resizing for coupled clock networks. ISCAS (5) 2003: 509-512 - [c18]Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen
Minimizing Inter-Clock Coupling Jitter. ISQED 2003: 333-338 - [c17]Win-Bin See, Pao-Ann Hsiung, Trong-Yen Lee, Sao-Jie Chen:
Software Platform for Embedded Software Development. RTCSA 2003: 545-557 - [c16]Jong-Sheng Cherng, Sao-Jie Chen
An Efficient Multi-Level Partitioning Algorithm for VLSI Circuits. VLSI Design 2003: 70- - 2002
- [j17]Jyh-Shan Chang, Sao-Jie Chen, Tzi-Dar Chiueh:
IETQ: An Incrementally Extensible Twisted Cube. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(5): 1140-1151 (2002) - [c15]Shuenn-Shi Chen, Wang-Dauh Tseng, Jin-Tai Yan, Sao-Jie Chen
Printed circuit board routing and package layout codesign. APCCAS (1) 2002: 155-158 - [c14]Trong-Yen Lee, Pao-Ann Hsiung, Sao-Jie Chen
TCN: Scalable Hierarchical Hypercubes. ICPADS 2002: 11-16 - [c13]Pao-Ann Hsiung, Trong-Yen Lee, Win-Bin See, Jih-Ming Fu, Sao-Jie Chen
VERTAF: An Object-Oriented Application Framework for Embedded Real-Time Systems. Symposium on Object-Oriented Real-Time Distributed Computing 2002: 322-329 - 2001
- [j16]Mao-Hsu Yen, Sao-Jie Chen
A Three-Stage One-Sided Rearrangeable Polygonal Switching Network. IEEE Trans. Computers 50(11): 1291-1294 (2001) - [j15]Mao-Hsu Yen, Sao-Jie Chen, Sanko Lan:
Symmetric and Programmable Multi-Chip Module for Low-Power Prototyping System. VLSI Design 12(2): 113-124 (2001) - [c12]Pao-Ann Hsiung, Win-Bin See, Trong-Yen Lee, Jih-Ming Fu, Sao-Jie Chen:
Formal Verification of Embedded Real-Time Software in Component-Based Application Frameworks. APSEC 2001: 71-78 - [c11]Jong-Sheng Cherng, Sao-Jie Chen:
A wire segment reassignment algorithm for minimizing crosstalk for strait-type river routing. ICECS 2001: 1305-1308 - [c10]Fong-Ming Shyu, Sao-Jie Chen:
A distributed and object-oriented framework for VLSI physical design automation. ISCAS (5) 2001: 77-80 - 2000
- [j14]Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai:
Efficient routability check algorithms for segmented channel routing. ACM Trans. Design Autom. Electr. Syst. 5(3): 735-747 (2000) - [j13]Sao-Jie Chen, Chung-Kuan Cheng:
Tutorial on VLSI Partitioning. VLSI Design 11(3): 175-218 (2000) - [c9]Jih-Ming Fu, Win-Bin See, Pao-Ann Hsiung, Jen-Ming Chao, Sao-Jie Chen:
A Java-Based Distributed System Framework for Real-Time Development. ICDCS Workshop on Distributed Real-Time Systems 2000: B31-B36
1990 – 1999
- 1999
- [j12]Chu Yu, Sao-Jie Chen
Design of an efficient VLSI architecture for 2-D discrete wavelet transforms. IEEE Trans. Consumer Electron. 45(1): 135-140 (1999) - [c8]Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho:
An Efficient Two-Level Partitioning Algorithm for VLSI Circuits. ASP-DAC 1999: 69-72 - [c7]Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai:
An Automatic Router for the Pin Grid Array Package. ASP-DAC 1999: 133-136 - [c6]Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai:
An Even Wiring Approach to the Ball Grid Array Package Routing. ICCD 1999: 303-306 - [c5]Chu Yu, Sao-Jie Chen:
Efficient VLSI architecture for 2-D inverse discrete wavelet transforms. ISCAS (3) 1999: 524-527 - [c4]Trong-Yen Lee, Pao-Ann Hsiung, Sao-Jie Chen:
A Case Study in Hardware-Software Codesign of Distributed Systems - Vehicle Parking Management System. PDPTA 1999: 2982-2987 - [c3]Jih-Ming Fu, Sao-Jie Chen:
Hardware-Software Coverification of Distributed Embedded Systems. PDPTA 1999: 2995-3001 - 1998
- [j11]Chia-Chun Tsai, Chwan-Ming Wang, Sao-Jie Chen
NEWS: a net-even-wiring system for the routing on a multilayer PGA package. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2): 182-189 (1998) - [j10]Pao-Ann Hsiung, Chung-Hwang Chen, Trong-Yen Lee, Sao-Jie Chen:
ICOS: an intelligent concurrent object-oriented synthesis methodology for multiprocessor systems. ACM Trans. Design Autom. Electr. Syst. 3(2): 109-135 (1998) - 1997
- [j9]Cheng-Hsing Yang, Chia-Chun Tsai, Jan-Ming Ho, Sao-Jie Chen:
Hmap: a fast mapper for EPGAs using extended GBDD hash tables. ACM Trans. Design Autom. Electr. Syst. 2(2): 135-150 (1997) - [c2]Pao-Ann Hsiung, Trong-Yen Lee, Sao-Jie Chen:
Object-Oriented Technology Transfer to Multiprocessor System-Level Synthesis. TOOLS (24) 1997: 284-293 - 1996
- [j8]Pao-Ann Hsiung, Sao-Jie Chen
PSM: an object-oriented synthesis approach to multiprocessor system design. IEEE Trans. Very Large Scale Integr. Syst. 4(1): 83-97 (1996) - 1995
- [j7]Jiann-Fu Lin, Win-Bin See, Sao-Jie Chen:
Performance Bounds on Scheduling Parallel Tasks with Communication Cost. IEICE Trans. Inf. Syst. 78-D(3): 263-268 (1995) - [j6]Jiann-Fu Lin, Sao-Jie Chen:
Performance Bounds on Scheduling Parallel Tasks with Setup Time on Hypercube Systems. Informatica (Slovenia) 19(3) (1995) - 1994
- [j5]Chia-Chun Tsai, Sao-Jie Chen:
A Linear Time Algorithm for Planar Moat Routing. J. Inf. Sci. Eng. 10(1): 111-127 (1994) - 1992
- [j4]Chia-Chun Tsai, Sao-Jie Chen
An H-V alternating router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(8): 976-991 (1992) - 1991
- [c1]Sung-Chuan Fang, Kuo-En Chang, Wu-Shiung Feng, Sao-Jie Chen:
Constrained via Minimization with Practical Considerations for Multi-Layer VLSI/PCB Routing Problems. DAC 1991: 60-65 - 1990
- [j3]Chia-Chun Tsai, Sao-Jie Chen
Generalized terminal connectivity problem for multilayer layout scheme. Comput. Aided Des. 22(7): 423-433 (1990) - [j2]Chia-Chun Tsai, Sao-Jie Chen, Wu-Shiung Feng:
An H-V Tile-Expansion Router. J. Inf. Sci. Eng. 6(3): 173-189 (1990) - [j1]Yu Hen Hu, Sao-Jie Chen
GM Plan: a gate matrix layout algorithm based on artificial intelligence planning techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8): 836-845 (1990)
Coauthor Index
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Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
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OpenAlex data
Load additional information about publications from .
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last updated on 2024-04-25 05:55 CEST by the dblp team
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