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Kazushi Kawamura
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2020 – today
- 2024
- [j16]Junnosuke Suzuki
, Jaehoon Yu
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision. IEEE Access 12: 2057-2073 (2024) - [j15]Shungo Kumazawa
Toward Improving Ensemble-Based Collaborative Inference at the Edge. IEEE Access 12: 6926-6940 (2024) - [j14]Satoru Jimbo
A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization. IEEE Access 12: 43660-43673 (2024) - [j13]Hikari Otsuka, Yasuyuki Okoshi, Ángel López García-Arias, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura:
Restricted Random Pruning at Initialization for High Compression Range. Trans. Mach. Learn. Res. 2024 (2024) - [c32]Junnosuke Suzuki, Mari Yasunaga, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Progressive Variable Precision DNN With Bitwise Ternary Accumulation. AICAS 2024: 377-381 - [c31]Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu:
Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow. ASPDAC 2024: 785-791 - [c30]Kyo Kuroki
Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization. GECCO 2024 - [c29]Yuki Ichikawa, Akihiro Shioda, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection. ICCE 2024: 1-2 - [c28]Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu:
Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA. ICCE 2024: 1-2 - [c27]Masato Watanabe, Shungo Kumazawa, Thiem Van Chu, Kazushi Kawamura, Jaehoon Yu, Masato Motomura:
Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA. ICCE 2024: 1-2 - [c26]Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
High Throughput Datapath Design for Vision Permutator FPGA Accelerator. ICCE 2024: 1-2 - [c25]Tsukasa Yamakura, Kazushi Kawamura, Masato Motomura, Thiem Van Chu:
ETreeNet: Ensemble Model Fusing Decision Trees and Neural Networks for Small Tabular Data. IJCNN 2024: 1-8 - [i2]Hikari Otsuka
Partial Search in a Frozen Network is Enough to Find a Strong Lottery Ticket. CoRR abs/2402.14029 (2024) - 2023
- [j12]Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura:
A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems. IEICE Trans. Inf. Syst. 106(12): 1969-1978 (2023) - [c24]Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura:
Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance. COOL CHIPS 2023: 1-3 - [c23]Thiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura:
Decision Forest Training Accelerator Based on Binary Feature Decomposition. FCCM 2023: 215 - [c22]Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Arias
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension. ISSCC 2023: 42-43 - [c21]Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Multicoated and Folded Graph Neural Networks With Strong Lottery Tickets. LoG 2023: 11 - [c20]Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura:
A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations. MCSoC 2023: 478-485 - [c19]Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. VLSI Technology and Circuits 2023: 1-2 - [i1]Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka
Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets. CoRR abs/2312.03236 (2023) - 2022
- [j11]Satoru Jimbo, Daiki Okonogi, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura:
A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers. IEICE Trans. Inf. Syst. 105-D(12): 2019-2031 (2022) - [c18]Yasuyuki Okoshi, Ángel López García-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu:
Multicoated Supermasks Enhance Hidden Networks. ICML 2022: 17045-17055 - [c17]Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura:
APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control. IPDPS Workshops 2022: 414-420 - [c16]Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet. ISSCC 2022: 1-3 - 2021
- [j10]Sho Kanamaru, Kazushi Kawamura, Shu Tanaka, Yoshinori Tomita, Nozomu Togawa:
Solving Constrained Slot Placement Problems Using an Ising Machine and Its Evaluations. IEICE Trans. Inf. Syst. 104-D(2): 226-236 (2021) - [j9]Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu:
ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training. Int. J. Netw. Comput. 11(2): 215-230 (2021) - [j8]Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu:
ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation. Int. J. Netw. Comput. 11(2): 338-353 (2021) - [j7]Kasho Yamamoto
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. IEEE J. Solid State Circuits 56(1): 165-178 (2021) - [c15]Thiem Van Chu, Ryuichi Kitajima, Kazushi Kawamura, Jaehoon Yu, Masato Motomura:
A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning. FPT 2021: 1-10 - [c14]Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura:
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner. HCS 2021: 1-21 - 2020
- [c13]Kento Hasegawa, Ryota Ishikawa, Makoto Nishizawa, Kazushi Kawamura, Masashi Tawada, Nozomu Togawa
FPGA-based Heterogeneous Solver for Three-Dimensional Routing. ASP-DAC 2020: 11-12 - [c12]Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training. CANDAR 2020: 146-152 - [c11]Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation. CANDAR 2020: 215-220
2010 – 2019
- 2019
- [j6]Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
An FPGA Implementation Method based on Distributed-register Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 12: 38-41 (2019) - [c10]Sho Kanamaru, Kazushi Kawamura, Shu Tanaka, Yoshinori Tomita, Hidetoshi Matsuoka, Kaoru Kawamura, Nozomu Togawa:
Mapping Constrained Slot-Placement Problems to Ising Models and its Evaluations by an Ising Machine. ICCE-Berlin 2019: 221-226 - [c9]Kento Hasegawa, Kazunari Takasaki, Makoto Nishizawa, Ryota Ishikawa, Kazushi Kawamura, Nozomu Togawa
Implementation of a ROS-Based Autonomous Vehicle on an FPGA Board. FPT 2019: 457-460 - 2018
- [c8]Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
A loop structure optimization targeting high-level synthesis of fast number theoretic transform. ISQED 2018: 106-111 - 2017
- [j5]Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(4): 1015-1028 (2017) - [c7]Yuya Hirai, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
A selector-based FFT processor and its FPGA implementation. ISOCC 2017: 88-89 - 2016
- [j4]Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1294-1310 (2016) - [j3]Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
Bi-Partitioning Based Multiplexer Network for Field-Data Extractors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1410-1414 (2016) - [c6]Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
A high-performance circuit design algorithm using data dependent approximation. ISOCC 2016: 95-96 - [c5]Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
Rotator-based multiplexer network synthesis for field-data extractors. SoCC 2016: 194-199 - 2015
- [j2]Koichi Fujiwara, Kazushi Kawamura, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1392-1405 (2015) - [c4]Kazushi Kawamura, Hiroki Shibasaki, Rubiyah Yusof, Yoshihisa Ishida:
An H∞ controller design based on the butterworth filter conversion. ASCC 2015: 1-6 - [c3]Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
Clock skew estimate modeling for FPGA high-level synthesis and its application. ASICON 2015: 1-4 - 2014
- [c2]Koichi Fujiwara, Shin-ya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs. APCCAS 2014: 244-247 - 2013
- [j1]Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(1): 312-321 (2013) - [c1]Kazushi Kawamura, Sho Tanaka, Masao Yanagisawa, Nozomu Togawa
A partial redundant fault-secure high-level synthesis algorithm for RDR architectures. ISCAS 2013: 1736-1739
Coauthor Index
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last updated on 2024-10-07 21:18 CEST by the dblp team
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