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ISED 2012: Kolkata, India
- International Symposium on Electronic System Design, ISEDs 2012, Kolkata, India, December 19-22, 2012. IEEE 2012, ISBN 978-1-4673-4704-4
- Rolf Drechsler
, Robert Wille
Synthesis of Reversible Circuits Using Decision Diagrams. 1-5 - Michael Kirkedal Thomsen, Holger Bock Axelsen, Robert Glück
Cleaning Up: Garbage-Free Reversible Circuits by Design Languages. 6-10 - Gerhard W. Dueck:
Synthesis of Toffoli Networks: Status and Challenges. 11-16 - D. Michael Miller, Zahra Sasanian:
Recent Developments on Mapping Reversible Circuits to Quantum Gate Libraries. 17-22 - R. Rajendran, P. V. Ramakrishna:
A Design of 6-bit 125-MS/s SAR ADC in 0.13-µm MM/RF CMOS Process. 23-27 - Sagar Mukherjee, Dipankar Saha, Posiba Mostafa, Sayan Chatterjee, Chandan Kumar Sarkar:
A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications. 28-32 - Vasantha M. H., Tonse Laxminidhi:
0.5 V, Low Power, 1 MHz Low Pass Filter in 0.18 µm CMOS Process. 33-37 - Laxmikandan Thangavelu, Ramakrishna P. V.:
Design Space Exploration and Synthesis of CMOS Low Noise Amplifiers. 38-42 - J. Selvakumar, Vidhyacharan Bhaskar, S. Narendran
FPGA Based Efficient Fast FIR Algorithm for Higher Order Digital FIR Filter. 43-47 - S. Rekha, Laxminidhi Tonse:
Effect of Finite Gain and Bandwidth of Feed-Forward Compensated OTA on Active-RC Integrators: A Case Study. 48-51 - C. V. Niras, Vinu Thomas:
Systolic Variable Length Architecture for Discrete Fourier Transform in Long Term Evolution. 52-55 - Rohit Srivastava, Nandini Mudgil, Gaurav Gupta, Hemanta Mondal:
SoC Time to Market Improvement through Device Driver Reuse: An Industrial Experience. 56-61 - Tapas Kumar Maiti, Subhadip Kundu, Arpita Dutta, Santanu Chattopadhyay:
Confidence Based Power Aware Testing. 62-66 - Kunal Banerjee, Chandan Karfa
A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques. 67-71 - K. Swaminathan, G. Lakshminarayanan
High Speed Generic Network Interface for Network on Chip Using Ping Pong Buffers. 72-76 - Gayadhar Panda
Analysis and Operation of FPGA-based Hybrid Active Power Filter for Harmonic Elimination in a Distribution System. 77-81 - Sumeet Agrawal, Pinal Engineer
FPGA Implementation of Particle Filter Based Object Tracking in Video. 82-86 - Deepak Chauhan, Sharad Kumar, Manoj Sharma:
Post Silicon Validation of Digital Radio Interfaces. 87-91 - Atin Mukherjee
Design of a Self-Reconfigurable Adder for Fault-Tolerant VLSI Architecture. 92-96 - Santhosh Keshavarapu, Saumya Jain, Manisha Pattanaik:
A New Assist Technique to Enhance the Read and Write Margins of Low Voltage SRAM Cell. 97-101 - Syed Ershad Ahmed, Sibi Abraham, Sreehari Veeramachaneni
A Modified Twin Precision Multiplier with 2D Bypassing Technique. 102-106 - Fateme Naderpour, Seok-Bum Ko
Improved Design of High-Radix Signed-Digit Adders. 107-110 - R. Uma, Jebashini Ponnian:
Systolic FIR Filter Design with Various Parallel Prefix Adders in FPGA: Performance Analysis. 111-115 - Kwen-Siong Chong, Joseph S. Chang, Idongesit E. Ebong, Yalcin Yilmaz, Pinaki Mazumder:
Comparison of FFT/IFFT Designs Utilizing Different Low Power Techniques. 116-119 - Sandip Ghosh, Prokash Ghosh
Dynamic Sharing of On-Chip Scratchpad Memory on Embedded Platforms. 120-124 - Xingxing Jin, Seok-Bum Ko
GPU-based Parallel Implementation of SAR Imaging. 125-129 - Subhramita Basak, Dipankar Saha, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar Sarkar:
Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme. 130-134 - S. Sivanantham
CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications. 135-139 - K. C. Cinnati Loi, Seok-Bum Ko
Improvements for High Performance Elliptic Curve Cryptosystem Processor over GF(2^163). 140-144 - Mousumi Saha, Souvik Das, Biplab K. Sikdar
High Speed Hardware for March C¯. 145-147 - Ashish Gupta, Gaurav Verma:
Bridging Validation and Automatic Test Equipment (ATE) Environment. 148-150 - Vikas Mahor, Akanksha Chouhan, Manisha Pattanaik:
A Process Variation Tolerant Low Contention Keeper Design for Wide Fan-In Dynamic OR Gate. 151-153 - Raju Hazari
Design of Hardware for Deterministic Nagel-Schreckenberg Traffic Model. 154-156 - Anirban De, Santwana Kumari, V. K. Khare, S. S. Pal, Anindya Sadhukhan, V. K. Meshram, S. K. Thakur, Subimal Saha:
Design, Development and Testing of a DSP Based Dynamic Voltage Restorer. 157-161 - Surajit Kumar Roy, Sobitri Chatterjee, Chandan Giri
Identifying Faulty TSVs in 3D Stacked IC during Pre-bond Testing. 162-166 - Vishal Shrivastav, Satya Gautam Vadlamudi, P. P. Chakrabarti, Dipankar Das, Purnendu Sinha:
Finding Critical Components in Embedded Control Systems Sensitive to Quality-Faults. 167-171 - Pradip Kumar Sahu, Ashish Sharma, Santanu Chattopadhyay:
Application Mapping Onto Mesh-of-Tree Based Network-on-Chip Using Discrete Particle Swarm Optimization. 172-176 - I. Hiteshwar Rao, Nafisa Ali Amir, Haresh Dagale, Joy Kuri:
e-SURAKSHAK: A Cyber-Physical Healthcare System with Service Oriented Architecture. 177-182 - Hoang M. Le, Daniel Große
From Requirements and Scenarios to ESL Design in SystemC. 183-187 - Sukanta Bhattacharjee, Ansuman Banerjee, Bhargab B. Bhattacharya:
Multiple Dilution Sample Preparation Using Digital Microfluidic Biochips. 188-192 - Deepak Bharti, Abhijit R. Asati
Design of a Static Current Simulator Using Device Matrix Approach. 193-197 - Brijesh Kumar, Brajesh Kumar Kaushik, Yuvraj Singh Negi:
Analysis of Contact Resistance Effect on Performance of Organic Thin Film Transistors. 198-202 - Sudip Roy, Bhargab B. Bhattacharya, Sarmishtha Ghoshal, Krishnendu Chakrabarty
Low-Cost Dilution Engine for Sample Preparation in Digital Microfluidic Biochips. 203-207 - Debaprasad Das, Sourav Das, Hafizur Rahaman
Design of 4-Bit Array Multiplier Using Multi-wall Carbon Nanotube Interconnects. 208-212 - Naushad Alam
The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Circuit Design Issues. 213-215 - Mamata Dalui, Biplab K. Sikdar
A Test Design for Quick Determination of Incoherency in Chip Multiprocessors' Cache Realizing MOESI Protocol. 216-220 - Prasun Ghosal, Tuhin Subhra Das:
SD2D: A Novel Routing Architecture for Network-on-Chip. 221-225 - Kamalika Datta, Indranil Sengupta, Hafizur Rahaman
Particle Swarm Optimization Based Circuit Synthesis of Reversible Logic. 226-230 - Rohith G.
Fractional Interpretation of Anomalous Diffusion and Semiconductor Equations. 231-235 - Manodipan Sahoo
Efficient and Compact Electrical Modeling of Multi Walled Carbon Nanotube Interconnects. 236-240 - Bibhash Sen, Manojit Dutta, Debajyoty Banik
Design of Fault Tolerant Reversible Arithmetic Logic Unit in QCA. 241-245 - Papia Manna, Dipak Kumar Kole, Hafizur Rahaman
Reversible Logic Circuit Synthesis Using Genetic Algorithm and Particle Swarm Optimization. 246-250 - Anwesha Banerjee
Electrooculogram Based Online Control Signal Generation for Wheelchair. 251-255 - Pranab Roy, Moudud Sohid, Sudipta Chakraborty, Hafizur Rahaman
System on Biochips: A New Design for Integration of Multiple DMFBs. 256-260 - Poornima Mittal, Yuvraj Singh Negi, R. K. Singh:
Analysis of Top and Bottom Contact Organic Transistor Performance for Different Technology Nodes. 261-263 - Soumyasree Bera, Arun Kumar Singh
Improvement in Target Detectability Using Spread Spectrum Radar in Dispersive Channel Condition. 264-266 - Rajdeep Mukherjee, Priyankar Ghosh, N. Sravan Kumar, Pallab Dasgupta, Ajit Pal:
Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed Framework. 267-271 - Shashikant Sharma
Signal Stepping Based Multimode Multi-threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders. 272-275 - Satarupa Bal, Anup Anurag
An Improved Soft Switching DC-DC Converter for Low Power PV Applications. 276-280 - Gunda Suman, B. V. S. Pavan Kumar, M. Sagar Kumar, B. Chitti Babu, K. R. Subhashini:
Modeling, Analysis and Design of Synchronous Buck Converter Using State Space Averaging Technique for PV Energy System. 281-285 - Deep Gupta
Enhancement of Medical Ultrasound Images Using Multiscale Discrete Shearlet Transform Based Thresholding. 286-290 - Hemant Agrawal, Yashpal Dutta, Sandeep Malik:
Performance Analysis of Offloading IPsec Processing to Hardware Based Accelerators. 291-294 - Jamil Galadanci, Rishad A. Shafik, Jimson Mathew, Amit Acharyya
A Closed-Loop Control Strategy for Glucose Control in Artificial Pancreas Systems. 295-299 - Parthajit Roy
A Delaunay Triangulation Preprocessing Based Fuzzy-Encroachment Graph Clustering for Large Scale GIS Data. 300-305 - Utpal Nandi
Fractal Image Compression Using Fast Context Independent HV Partitioning Scheme. 306-308 - Vishram Mishra, Chiew Tong Lau, Syin Chan, Ashish Kumar:
Energy Aware Spectrum Decision Framework for Cognitive Radio Networks. 309-313 - Soumya Maity, Padmalochan Bera, S. K. Ghosh:
Policy Based ACL Configuration Synthesis in Enterprise Networks: A Formal Approach. 314-318
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