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Biplab K. Sikdar
Biplab Kumar Sikdar
Person information
- affiliation: Indian Institute of Engineering Science and Technology, Department of Computer Science and Technology, Howrah, India
- affiliation (PhD 2003): Bengal Engineering and Science University, Shibpur, India
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2020 – today
- 2024
- [j37]Baisakhi Das, Mamata Dalui, Mousumi Saha, Kasturi Ghosh, Nilanjana Das, Biplab K. Sikdar:
Exploring Periodic Boundary Cellular Automaton Rules for One and Two Fixed Points. Complex Syst. 33(1): 31-60 (2024) - [j36]Mahabub Hasan Mahalat
, Shyam Subba, Anindan Mondal, Biplab K. Sikdar, Rajat Subhra Chakraborty, Bibhash Sen:
CAPUF: Design of a configurable circular arbiter PUF with enhanced security and hardware efficiency. Integr. 95: 102113 (2024) - [c105]Avishek Choudhury, Brototi Mondal, Kolin Paul, Biplab K. Sikdar:
LLC Block Reuse Predictor Design using Deep Learning to Mitigate Soft Error in Multicore. VLSID 2024: 690-695 - 2023
- [j35]Avishek Choudhury
Energy efficiency in multicore shared cache by fault tolerance using a genetic algorithm based block reuse predictor. Microprocess. Microsystems 101: 104864 (2023) - 2022
- [j34]Sutapa Sarkar
Cellular automata based multi-bit stuck-at fault diagnosis for resistive memory. Frontiers Inf. Technol. Electron. Eng. 23(7): 1110-1126 (2022) - [c104]Baisakhi Das
Identification of Periodic Boundary SACA Rules Exploring NSRT Diagram. ACRI 2022: 29-39 - [c103]Amit Kumar Pramanik
Performance Analysis of Regular Clocking Based Quantum-Dot Cellular Automata Logic Circuit: Fault Tolerant Approach. ACRI 2022: 185-198 - 2021
- [j33]Bidesh Chakraborty
Synthesis of Scalable Single Length Cycle, Single Attractor Cellular Automata in Linear Time. Complex Syst. 30(3): 415-439 (2021) - [j32]Supreeti Kamilya, Sukanta Das, Biplab K. Sikdar:
Simulation of Non-uniform Cellular Automata by Classical Cellular Automata and Its Application in Embedded Systems. J. Cell. Autom. 16(1-2): 61-86 (2021) - [j31]Nilanjana Das
A trojan framework in AES core to evade state-of-the-art HT detection schemes. Microelectron. J. 111: 105023 (2021) - 2020
- [j30]Avishek Choudhury
Modeling Remapping Based Fault Tolerance Techniques for Chip Multiprocessor Cache with Design Space Exploration. J. Electron. Test. 36(1): 59-73 (2020) - [c102]Nilanjana Das, Joy Halder, Baisakhi Das, Biplab K. Sikdar:
Exploring Hard to Detect Sequential Hardware Trojans. VDAT 2020: 1-6 - [c101]Jayanta Paul
Evaluation of Face Recognition Schemes for Low-computation IoT System Design. VDAT 2020: 1-6
2010 – 2019
- 2019
- [j29]Supreeti Kamilya, Sumit Adak, Sukanta Das, Biplab K. Sikdar:
SACAs: (Non-uniform) Cellular Automata that Converge to a Single Fixed Point. J. Cell. Autom. 14(1-2): 27-49 (2019) - [j28]Bidesh Chakraborty
Cellular Automata Based Test Design for Coherence Verification in 3D Caches. J. Circuits Syst. Comput. 28(9): 1950148:1-1950148:25 (2019) - [c100]Avishek Choudhury, Brototi Mondal, Biplab K. Sikdar:
Latency Aware Fault Tolerant Cache in Multicore Using Dynamic Remapping Clusters. ATS 2019: 79 - [c99]Avishek Choudhury, Biplab K. Sikdar:
CORE-VR: A Coherence and Reusability Aware Low Voltage Fault Tolerant Cache in Multicore. DFT 2019: 1-4 - [c98]Avishek Choudhury, Biplab K. Sikdar:
Soft Error Resilience in Chip Multiprocessor Cache using a Markov Model Based Re-usability Predictor. ICCD 2019: 468-476 - [c97]Baisakhi Das, Nilanjana Das, Biplab K. Sikdar:
Effect of Trojans on Write Data Access in Memory. ISED 2019: 1-5 - 2018
- [j27]Bidesh Chakraborty
Design of a Reliable Cache System for Heterogeneous CMPs. J. Circuits Syst. Comput. 27(14): 1850219:1-1850219:28 (2018) - [c96]Baisakhi Das, Mamata Dalui, Anupama Mondal, Salma Mandi, Nilanjana Das, Biplab K. Sikdar
Evaluation of Misspeculation Impact on Chip-Multiprocessors Power Overhead. ICSCA 2018: 129-133 - [c95]Avishek Choudhury, Brototi Mondal, Biplab K. Sikdar
ReMiT: Redundancy Migration for Latency Aware Fault Tolerant Cache Design in Multicore. ISED 2018: 80-84 - [c94]Nilanjana Das, Mousumi Saha, Biplab K. Sikdar
Hard to Detect Combinational Hardware Trojans. ISED 2018: 194-198 - [c93]Baisakhi Das, Nilanjana Das, Biplab K. Sikdar
Stuck-At 0/1 Trojans on Return Address Stack. ISED 2018: 210-214 - [c92]Avishek Choudhury, Biplab K. Sikdar
Modeling & Analysis of Redundancy Based Fault Tolerance for Permanent Faults in Chip Multiprocessor Cache. VLSID 2018: 115-120 - 2017
- [j26]Rajdeep Kumar Nath, Bibhash Sen, Biplab K. Sikdar
Optimal synthesis of QCA logic circuit eliminating wire-crossings. IET Circuits Devices Syst. 11(3): 201-208 (2017) - [j25]Baisakhi Das, Biplab K. Sikdar:
Evaluating impact on CMPs' power for design inaccuracy diagnosis. Int. J. Comput. Appl. Technol. 56(3): 198-209 (2017) - [j24]Mrinal Goswami
Design of Testable Adder in Quantum-dot Cellular Automata with Fault Secure Logic. Microelectron. J. 60: 1-12 (2017) - [j23]Mamata Dalui, Biplab K. Sikdar
A cellular automata based self-correcting protocol processor for scalable CMPs. Microelectron. J. 62: 108-119 (2017) - [c91]Mousumi Saha, Baisakhi Das, Biplab K. Sikdar
Periodic boundary cellular automata based test structure for memory. EWDTS 2017: 1-6 - [c90]Sutapa Sarkar, Mousumi Saha, Biplab K. Sikdar
Multi-bit fault tolerant design for resistive memories through dynamic partitioning. EWDTS 2017: 1-6 - [c89]Avishek Choudhury, Biplab K. Sikdar
CIFR: A complete in-place fault remapping strategy for CMP cache using dynamic reuse distance. ISED 2017: 1-5 - [c88]Avishek Choudhury, Biplab K. Sikdar
Performance Analysis of Disability Based Fault Tolerance Techniques for Permanent Faults in Chip Multiprocessors. VDAT 2017: 217-224 - [c87]Bidesh Chakraborty
Design of Coherence Verification Unit for Heterogeneous CMPs Integrating Update and Invalidate Protocols. VLSID 2017: 115-120 - 2016
- [j22]Bibhash Sen
On the reliability of majority logic structure in quantum-dot cellular automata. Microelectron. J. 47: 7-18 (2016) - [j21]Saha Mousumi
A cellular automata based highly accurate memory test hardware realizing March C-. Microelectron. J. 52: 91-103 (2016) - [j20]Mamata Dalui
A Cache System Design for CMPs with Built-In Coherence Verification. VLSI Design 2016: 8093614:1-8093614:16 (2016) - [c86]Mrinal Goswami, Bibhash Sen, Biplab K. Sikdar
Design of low power 5-input majority voter in quantum-dot cellular automata with effective error resilience. ISED 2016: 101-105 - [c85]Baisakhi Das, Supreeti Kamilya
Design of CA based scheme for evenhanded data migration in CMPs. ISED 2016: 117-121 - [c84]Mousumi Saha, Sutapa Sarkar, Biplab K. Sikdar
Cellular automata based fault tolerant resistive memory design. ISED 2016: 176-180 - [c83]Mamata Dalui, Tannishtha Som
MASI: An eviction aware cache coherence protocol for CMPs. ISED 2016: 249-253 - [c82]Bidesh Chakraborty
CA based protocol processor for heterogeneous CMPs. ISED 2016: 254-258 - [c81]Bidesh Chakraborty
Design of coherence verification unit for CMPs realizing dragon protocol. VDAT 2016: 1-6 - [c80]Bibhash Sen, Rajdeep Kumar Nath, Rijoy Mukherjee, Yashraj Sahu, Biplab K. Sikdar
Towards Designing Reliable Universal QCA Logic in the Presence of Cell Deposition Defect. VLSID 2016: 575-576 - 2015
- [j19]Bibhash Sen, Mrinal Goswami
Towards modular design of reliable quantum-dot cellular automata logic circuit using multiplexers. Comput. Electr. Eng. 45: 42-54 (2015) - [j18]Bibhash Sen
Towards the hierarchical design of multilayer QCA logic circuit. J. Comput. Sci. 11: 233-244 (2015) - [c79]Saha Mousumi, Biplab K. Sikdar
A Cellular Automata Based Fault Tolerant Approach in Designing Test Hardware for L1 Cache Module. ISVLSI 2015: 497-502 - [c78]Bidesh Chakraborty
Design of coherence verification unit for heterogeneous CMPs. VDAT 2015: 1-6 - [c77]Saha Mousumi, Navneet Kumar Gautam, Biplab K. Sikdar
A fault tolerant test hardware for L1 cache module in tile CMPs architecture. VDAT 2015: 1-6 - [c76]Rajdeep Kumar Nath, Bibhash Sen, Rachit Daga, Nilesh Chakraborty, Harsh Tibrewal, Biplab K. Sikdar
Fault masking in Quantum-dot cellular automata using prohibitive logic circuit. VDAT 2015: 1-5 - 2014
- [j17]Bibhash Sen, Manojit Dutta, Samik Some, Biplab K. Sikdar
Realizing Reversible Computing in QCA Framework Resulting in Efficient Design of Testable ALU. ACM J. Emerg. Technol. Comput. Syst. 11(3): 30:1-30:22 (2014) - [j16]Bibhash Sen
Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing. Microelectron. J. 45(2): 239-248 (2014) - [j15]Bibhash Sen
Modular Design of testable reversible ALU by QCA multiplexer with increase in programmability. Microelectron. J. 45(11): 1522-1532 (2014) - [c75]Mamata Dalui, Biplab K. Sikdar
CA Based Scalable Protocol Processor for Chip Multiprocessors. ISED 2014: 161-165 - [c74]Bibhash Sen, Rijoy Mukherjee, Rajdeep Kumar Nath, Biplab K. Sikdar
Design of Fault Tolerant Universal Logic in QCA. ISED 2014: 166-170 - 2013
- [c73]Mamata Dalui, Biplab K. Sikdar
Design of directory based cache coherence protocol verification logic in CMPs around TACA. HPCS 2013: 318-325 - [c72]Saha Mousumi, Biplab K. Sikdar
A cellular automata based design of self testable hardware for March C-. HPCS 2013: 333-338 - [c71]Mamata Dalui, Keshav Gupta, Biplab K. Sikdar
Directory based cache coherence verification logic in CMPs cache system. MES 2013: 33-40 - [c70]Bibhash Sen, Mrinal Goswami
Design of Sequential Circuits in Multilayer QCA Structure. ISED 2013: 21-25 - [c69]Baisakhi Das, Nirmalya Sundar Maiti, Sukanta Das, Mousumi Saha, Biplab K. Sikdar
Design of an Efficient Scheme for Data Migration in Chip-Multiprocessors. ISED 2013: 167-171 - [i1]Sukanta Das, Biplab K. Sikdar:
Analysis and synthesis of nonlinear reversible cellular automata in linear time. CoRR abs/1311.6879 (2013) - 2012
- [j14]Nirmalya Sundar Maiti, Soumyabrata Ghosh, Biplab K. Sikdar, Parimal Pal Chaudhuri:
Rule Vector Graph (RVG) To Design Linear Time Algorithm for Identifying the Invertibility of Periodic-Boundary Three Neighborhood Cellular Automata. J. Cell. Autom. 7(4): 335-362 (2012) - [j13]Nazma Naskar, Sukanta Das, Biplab K. Sikdar:
Characterization of Nonlinear Cellular Automata Having Only Single Length Cycle Attractors. J. Cell. Autom. 7(5-6): 431-453 (2012) - [c68]Sukanta Das, Avik Chakraborty, Biplab K. Sikdar:
Counting Cycles in Reversible Cellular Automata. ACRI 2012: 11-19 - [c67]Nasiruddin Khan, Ilora Maity
A Cellular Automata Based Scheme for Energy Efficient Fault Diagnosis in WSN. ACRI 2012: 234-243 - [c66]Sukanta Das, Anindita Sarkar, Biplab K. Sikdar:
Synthesis of Reversible Asynchronous Cellular Automata for Pattern Generation with Specific Hamming Distance. ACRI 2012: 643-652 - [c65]Mousumi Saha, Souvik Das, Biplab K. Sikdar
High Speed Hardware for March C¯. ISED 2012: 145-147 - [c64]Mamata Dalui, Biplab K. Sikdar
A Test Design for Quick Determination of Incoherency in Chip Multiprocessors' Cache Realizing MOESI Protocol. ISED 2012: 216-220 - [c63]Bibhash Sen, Manojit Dutta, Debajyoty Banik
Design of Fault Tolerant Reversible Arithmetic Logic Unit in QCA. ISED 2012: 241-245 - [c62]Mamata Dalui, Biplab K. Sikdar
An Efficient Test Design for CMPs Cache Coherence Realizing MESI Protocol. VDAT 2012: 89-98 - [c61]Bibhash Sen
An Efficient Multiplexer in Quantum-dot Cellular Automata. VDAT 2012: 350-351 - 2011
- [j12]Soumyabrata Ghosh, Nirmalya Sundar Maiti, Parimal Pal Chaudhuri, Biplab K. Sikdar:
On Invertible Three Neighborhood Null-Boundary Uniform Cellular Automata. Complex Syst. 20(1) (2011) - [c60]Indrajit Banerjee
DFDNM: A Distributed Fault Detection and Node Management Scheme for Wireless Sensor Network. ACC (3) 2011: 68-81 - [c59]Gunjan Bhattacharya, Ilora Maity
Exploring Impact of Faults on Branch Predictors' Power for Diagnosis of Faulty Module. Asian Test Symposium 2011: 226-231 - [c58]Mamata Dalui, Biplab K. Sikdar
An Efficient Test Design for Verification of Cache Coherence in CMPs. DASC 2011: 328-334 - [c57]Baisakhi Das, Gunjan Bhattacharya, Ilora Maity
Impact of Inaccurate Design of Branch Predictors on Processors' Power Consumption. DASC 2011: 335-342 - [c56]Bibhash Sen, Divyam Saran, Mousumi Saha, Biplab K. Sikdar
Synthesis of Reversible Universal Logic around QCA with Online Testability. ISED 2011: 236-241 - [c55]Ilora Maity
A cellular automata based scheme for diagnosis of faulty nodes in WSN. SMC 2011: 1212-1217 - 2010
- [j11]Sukanta Das, Biplab K. Sikdar
A Scalable Test Structure for Multicore Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(1): 127-137 (2010) - [c54]Nirmalya Sundar Maiti, Soumyabrata Ghosh
Programmable Cellular Automata (PCA) Based Advanced Encryption Standard (AES) Hardware Architecture. ACRI 2010: 271-274 - [c53]Sukanta Das, Nazma Naskar, Sukanya Mukherjee, Mamata Dalui, Biplab K. Sikdar
Characterization of CA Rules for SACA Targeting Detection of Faulty Nodes in WSN. ACRI 2010: 300-311 - [c52]Bibhash Sen
Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit. DSD 2010: 613-620 - [c51]Bibhash Sen, Mamata Dalui, Biplab K. Sikdar
Introducing universal QCA logic gate for synthesizing symmetric functions with minimum wire-crossings. ICWET 2010: 828-833 - [c50]Indrajit Banerjee
SSMCA: CA based Segmented Sensor Network Management scheme. SMC 2010: 177-184 - [c49]Mamata Dalui, Suhrid Bakshi, Biplab K. Sikdar
CA based quick consensus in distributed system through network partitioning. SMC 2010: 684-691
2000 – 2009
- 2009
- [c48]Sukanta Das, Biplab K. Sikdar
CA Based Built-In Self-Test Structure for SoC. Asian Test Symposium 2009: 3-8 - [c47]Sukanta Das, Nazma Naskar, Sukanya Mukherjee, Biplab K. Sikdar:
CA Rules Identification for Efficient Design of Pattern Classifier. CSC 2009: 336-341 - [c46]Sukanta Das, Sukanya Mukherjee, Nazma Naskar, Biplab K. Sikdar
Modeling Single Length Cycle Nonlinear Cellular Automata for Pattern Recognition. NaBIC 2009: 198-203 - [c45]Debashis Moitra, Prosenjit Das, Pushan Mitra, Biplab Kumar Sikdar
Cost Optimal Design of 3-D Steel Building Frames using CA-LFSR. NaBIC 2009: 788-793 - [c44]Biplab Kumar Sikdar
Quick Consensus Through Early Disposal of Faulty Processes. SMC 2009: 1989-1994 - [c43]Sukanta Das, Meghnath Saha, Biplab Kumar Sikdar
A Cellular Automata Based Model for Traffic in Congested City. SMC 2009: 2397-2402 - [c42]Sukanta Das, Sukanya Mukherjee, Nazma Naskar, Biplab K. Sikdar
Characterization of Single Cycle CA and its Application in Pattern Classification. AUTOMATA 2009: 181-203 - [c41]Sukanta Das, Biplab K. Sikdar
Characterization of 1-d Periodic Boundary Reversible CA. AUTOMATA 2009: 205-227 - 2008
- [j10]Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri:
Exploring Cycle Structures of Additive Cellular Automata. Fundam. Informaticae 87(2): 137-154 (2008) - [j9]Debashis Moitra, Sandip Dhar, J. M. Mallick, S. Sadhu, Biplab K. Sikdar:
Cellular Automata Based Design of Cost Optimal Steel Building Frames. Fundam. Informaticae 87(2): 227-245 (2008) - [c40]Sukanta Das, Chandrama Shaw, Biplab K. Sikdar
Exploring CAState Space to Synthesize Cellular Automata with Specified Attractor Set. ACRI 2008: 152-159 - [c39]Sukanta Das, Biplab K. Sikdar
Characterization of Non-reachable States in Irreversible CAState Space. ACRI 2008: 160-167 - 2007
- [c38]Sukanta Das, DasBit Sipra, Biplab K. Sikdar:
CA Based Data Servicing In Cellular Mobile Network. ICWN 2007: 280-286 - [c37]Debashis Moitra, Sandip Dhar, J. M. Mallick, Biplab K. Sikdar:
Cellular Automata Model for Cost Optimal Design of Steel Building Frames. IICAI 2007: 1440-1455 - [c36]Hafizur Rahaman
Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). VTS 2007: 422-430 - 2006
- [c35]Sukanta Das, Biplab K. Sikdar:
Classification of CA Rules Targeting Synthesis of Reversible Cellular Automata. ACRI 2006: 68-77 - [c34]Chandrama Shaw, Sukanta Das, Biplab K. Sikdar:
Cellular Automata Based Encoding Technique for Wavelet Transformed Data Targeting Still Image Compression. ACRI 2006: 141-146 - [c33]Biplab K. Sikdar
Study of N-Detectability in QCA Designs. ATS 2006: 183-188 - [c32]Indrajit Banerjee
An Energy Effilcient Monitoring of Ad-Hoc Sensor Network with Cellular Automata. SMC 2006: 5100-5105 - 2005
- [j8]Biplab K. Sikdar
A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area. J. Electron. Test. 21(1): 83-93 (2005) - [j7]Sukanta Das, Anirban Kundu
Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time. J. Electron. Test. 21(1): 95-107 (2005) - [j6]Biplab K. Sikdar
Fault diagnosis of VLSI circuits with cellular automata based pattern classifier. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 1115-1131 (2005) - [c31]Sukanta Das, Hafizur Rahaman
Cost Optimal Design of Nonlinear CA based PRPG for Test Applications. Asian Test Symposium 2005: 284-287 - [c30]Biplab K. Sikdar
Synthesis of Testable Finite State Machine Through Decomposition. Asian Test Symposium 2005: 398-403 - [c29]Sukanta Das, Sipra Das Bit, Biplab K. Sikdar:
Non-linear cellular automata based design of query processor for mobile network. SMC 2005: 2751-2756 - [c28]Biplab K. Sikdar, Sukanta Das, Samir Roy, Niloy Ganguly, Debesh K. Das:
Cellular Automata Based Test Structures with Logic Folding. VLSI Design 2005: 71-74 - 2004
- [j5]Biplab K. Sikdar
Generation of test patterns without prohibited pattern set. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1650-1660 (2004) - [j4]Niloy Ganguly, Pradipta Maji
Design and characterization of cellular automata based associative memory for pattern recognition. IEEE Trans. Syst. Man Cybern. Part B 34(1): 672-678 (2004) - [c27]Pradipta Maji, Biplab K. Sikdar, Parimal Pal Chaudhuri:
Cellular Automata Evolution for Distributed Data Mining. ACRI 2004: 40-49 - [c26]Chandrama Shaw, Pradipta Maji, Sourav Saha
Cellular Automata Based Encompression Technology for Voice Data. ACRI 2004: 258-267 - [c25]Pradipta Maji, Biplab K. Sikdar, Parimal Pal Chaudhuri:
Cellular Automata Evolution for Pattern Classification. ACRI 2004: 660-669 - [c24]Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri:
Characterization of Reachable/Nonreachable Cellular Automata States. ACRI 2004: 813-822 - [c23]Sukanta Das, Debdas Dey, Subhayan Sen, Biplab K. Sikdar, Parimal Pal Chaudhuri:
An efficient design of non-linear CA based PRPG for VLSI circuit testing. ASP-DAC 2004: 110-112 - [c22]Sukanta Das, Anirban Kundu, Biplab K. Sikdar:
Nonlinear CA Based Design of Test Set Generator Targeting Pseudo-Random Pattern Resistant Faults. Asian Test Symposium 2004: 196-201 - [c21]Sukanta Das, Biplab K. Sikdar
Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores. Asian Test Symposium 2004: 331-334 - [c20]Chandrama Shaw, Biplab K. Sikdar, N. C. Maiti:
CA Based Document Compression Technology. ICONIP 2004: 679-685 - 2003
- [j3]Pradipta Maji, Chandrama Shaw, Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri:
Theory and Application of Cellular Automata For Pattern Classification. Fundam. Informaticae 58(2003): 321-354 (2003) - [c19]Samir Roy, Ujjwal Maulik, Sanghamitra Bandyopadhyay, Subhadip Basu, Biplab Kumar Sikdar:
Efficient BIST design for sequential machines using FiF-FoF values in machine states. ASP-DAC 2003: 875-878 - [c18]Sukanta Das, Anirban Kundu
Non-Linear Celluar Automata Based PRPG Design (Without Prohibited Pattern Set) In Linear Time Complexity. Asian Test Symposium 2003: 78-83 - [c17]Samir Roy, Biplab K. Sikdar
Power Conscious BIST Design for Sequential Circuits Using ghost-FSM. Asian Test Symposium 2003: 190-195 - [c16]Samir Roy, Ujjwal Maulik
Exploiting Ghost-FSMs as a BIST Structure for Sequential Machines. VLSI Design 2003: 155-160 - [c15]Sukanta Das, Niloy Ganguly, Biplab K. Sikdar
Design Of A Universal BIST (UBIST) Structure. VLSI Design 2003: 161-166 - 2002
- [j2]Niloy Ganguly, Pradipta Maji
Generalized Multiple Attractor Cellular Automata (GMACA) Model for Associative Memory. Int. J. Pattern Recognit. Artif. Intell. 16(7): 781-796 (2002) - [j1]Biplab K. Sikdar
Design of hierarchical cellular automata for on-chip test pattern generator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12): 1530-1539 (2002) - [c14]Niloy Ganguly, Pradipta Maji, Sandip Dhar, Biplab K. Sikdar, Parimal Pal Chaudhuri:
Evolving Cellular Automata as Pattern Classifier. ACRI 2002: 56-68 - [c13]Niloy Ganguly, Pradipta Maji, Arijit Das, Biplab K. Sikdar, Parimal Pal Chaudhuri:
Characterization of Non-linear Cellular Automata Model for Pattern Recognition. AFSS 2002: 214-220 - [c12]Niloy Ganguly, Anindyasundar Nandi, Sukanta Das, Biplab K. Sikdar
An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS). Asian Test Symposium 2002: 260-265 - [c11]Samir Roy, Biplab K. Sikdar
Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. ASP-DAC/VLSI Design 2002: 671-676 - [c10]Niloy Ganguly, Biplab K. Sikdar
Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS). ASP-DAC/VLSI Design 2002: 689- - 2001
- [c9]Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri:
Cellular automata as a built in self test structure. ASP-DAC 2001: 319-324 - [c8]Biplab K. Sikdar
Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis. Asian Test Symposium 2001: 285- - [c7]Biplab K. Sikdar
Multiple Attractor Cellular Automata for Hierarchical Diagnosis of VLSI Circuits. Asian Test Symposium 2001: 385-390 - [c6]Niloy Ganguly, Arijit Das, Pradipta Maji, Biplab K. Sikdar, Parimal Pal Chaudhuri:
Evolving Cellular Automata Based Associative Memory for Pattern Recognition. HiPC 2001: 115-124 - [c5]Biplab K. Sikdar
Hierarchical Cellular Automata As An On-Chip Test Pattern Generator. VLSI Design 2001: 403- - [c4]Biplab K. Sikdar, Purnabha Majumder, Parimal Pal Chaudhuri, Niloy Ganguly:
Design Of Multiple Attractor Gf (2p) Cellular AutomataFor Diagnosis Of Vlsi Circuits. VLSI Design 2001: 454-459 - 2000
- [c3]Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury, Kolin Paul, Biplab K. Sikdar:
Theory and Applications of Cellular Automata for VLSI Design and Testing. VLSI Design 2000: 4 - [c2]Kolin Paul, Ranadeep Ghosal, Biplab K. Sikdar, Santashil Pal Chaudhuri, Dipanwita Roy Chowdhury:
GF(2p) CA Based Vector Quantization for Fast Encoding of Still Images. VLSI Design 2000: 140-143 - [c1]Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee:
Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator. VLSI Design 2000: 556-561
Coauthor Index
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last updated on 2024-10-07 21:23 CEST by the dblp team
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