default search action
FPGA 2022: Virtual Event, USA
- Michael Adler, Paolo Ienne:
FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022 - 1 March 2022. ACM 2022, ISBN 978-1-4503-9149-8
Session 1: Architecture and CAD
- Licheng Guo, Pongstorn Maidee
, Yun Zhou
RapidStream: Parallel Physical Implementation of FPGA HLS Designs. 1-12 - King Lok Chung
How to Shrink My FPGAs - Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA Fabrics. 13-23 - Yue Zha, Jing Li:
Revisiting PathFinder Routing Algorithm. 24-34 - Herman Schmit, Matthew Denton:
Multi-input Serial Adders for FPGA-like Computational Fabric. 35-41 - Qingcheng Xiao, Yun Liang:
Towards Agile DNN Accelerator Design Using Incremental Synthesis on FPGAs. 42-48
Keynote 1
- Zsolt Tokei:
Logic Scaling Options for the Next 10 Years: From FinFet to CFET, from Dual Damascene to Semi Damascene. 49
Poster Session 1
- Mingqiang Huang, Yucen Liu, Quan Cheng, Shuxin Yang, Kai Li, Junyi Luo, Zhengke Yang, Qiufeng Li, Hao Yu, Changhai Man:
A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA. 50 - Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong:
Automated Accelerator Optimization Aided by Graph Neural Networks. 50 - Rashmi Agrawal, Ji Yang, Haris Javaid:
Efficient FPGA-based ECDSA Verification Engine For Permissioned Blockchains. 50 - Tian Ye, Rajgopal Kannan, Viktor K. Prasanna:
End-to-End Acceleration of Homomorphic Encrypted CNN Inference on FPGAs. 51 - Maria Rafaela Gkeka, Alexandros Patras, Nikolaos Tavoularis, Stylianos Piperakis, Emmanouil Hourdakis, Panos E. Trahanias, Christos D. Antonopoulos, Spyros Lalis, Nikolaos Bellas:
FPGA Accelerators for Robust Visual SLAM on Humanoid Robots. 51 - Yanqi Liu, Anthony Opipari, Théo Guérin, Ruth Iris Bahar:
Hardware Acceleration of Nonparametric Belief Propagation for Efficient Robot Manipulation. 51 - Rakin Muhammad Shadab, Yu Zou, Sanjay Gandham, Amro Awad, Mingjie Lin:
HMT: A Hardware-Centric Hybrid Bonsai Merkle Tree Algorithm for High-Performance Authentication. 52 - Aman Arora
MathRAMs: Configurable Fused Compute-Memory Blocks for FPGAs. 52 - Martha Barker, Stephen A. Edwards, Martha A. Kim
Synthesized Garbage Collection for FPGA Accelerators. 53
Session 2: High-Level Tools and Abstractions
- Yixiao Du
High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS: A Case Study on SpMV. 54-64 - Linghao Song
Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication. 65-77 - Shaojie Xiang, Yi-Hsiang Lai, Yuan Zhou, Hongzheng Chen
HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs. 78-88 - Jianyi Cheng, John Wickerson, George A. Constantinides:
Finding and Finessing Static Islands in Dynamically Scheduled Circuits. 89-100
Session 3: Machine Learning
- Erwei Wang, James J. Davis, Georgios-Ilias Stavrou
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. 101-111 - Yu Gong, Zhihan Xu, Zhezhi He, Weifeng Zhang, Xiaobing Tu, Xiaoyao Liang, Li Jiang:
N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores. 112-122 - Yi-Chien Lin, Bingyi Zhang, Viktor K. Prasanna:
HP-GNN: Generating High Throughput GNN Training Implementation on CPU-FPGA Heterogeneous Platform. 123-133 - Mengshu Sun, Zhengang Li, Alec Lu, Yanyu Li, Sung-En Chang, Xiaolong Ma, Xue Lin, Zhenman Fang:
FILM-QNN: Efficient FPGA Acceleration of Deep Neural Networks with Intra-Layer, Mixed-Precision Quantization. 134-145 - Shinhaeng Kang, Sukhan Lee, Byeongho Kim, Hweesoo Kim, Kyomin Sohn, Nam Sung Kim, Eojin Lee:
An FPGA-based RNN-T Inference Accelerator with PIM-HBM. 146-152
Keynote 2
- Satnam Singh:
The Virtuous Cycles of Determinism: Programming Groq's Tensor Streaming Processor. 153
Poster Session 2
- Bingyi Zhang, Hanqing Zeng, Viktor K. Prasanna:
DecGNN: A Framework for Mapping Decoupled GNN Models onto CPU-FPGA Heterogeneous Platform. 154 - Jonas Ney, Sebastian Dörner, Matthias Herrmann, Mohammad Hassani Sadi, Jannis Clausius, Stephan ten Brink, Norbert Wehn:
FPGA-based Trainable Autoencoder for Communication Systems. 154 - Zhenyu Xu, Thomas Mauldin, Qing Yang, Tao Wei:
Highly Scalable Runtime Countermeasure Against Microprobing Attacks on Die-to-Die Interconnections in System-in-Package. 154 - Yuanlong Xiao, André DeHon:
HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers. 155 - Mohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami:
MAQO: A Scalable Many-Core Annealer for Quadratic Optimization on a Stratix 10 FPGA. 155 - Yukui Luo, Yuheng Zhang, Shijin Duan, Xiaolin Xu:
An Integrity Checking Framework for AXI Protocol in Multi-tenant FPGA. 155 - Atefeh Sohrabizadeh, Yuze Chi, Jason Cong:
SPA-GCN: Efficient and Flexible GCN Accelerator with Application for Graph Similarity Computation. 156 - Jiafeng Xie, Pengzhou He, Tianyou Bao
Ultra Low-Complexity Implementation of Binary Ring-LWE based Post-Quantum Cryptography on FPGA Platform. 156 - Seyed Alireza Damghani, Kenneth B. Kent:
Yosys+Odin-II: The Odin-II Partial Mapper with Yosys Coarse-grained Netlists in VTR. 157
Session 4: Applications
- Yizhao Gao
REMOT: A Hardware-Software Architecture for Attention-Guided Multi-Object Tracking with Dynamic Vision Sensors on FPGAs. 158-168 - Ce Guo, Wayne Luk:
Accelerating Constraint-Based Causal Discovery by Shifting Speed Bottleneck. 169-179 - Marius Knaust, Enrico Seiler, Knut Reinert
Co-Design for Energy Efficient and Fast Genomic Search: Interleaved Bloom Filter on FPGA. 180-189 - Yuze Chi, Licheng Guo, Jason Cong:
Accelerating SSSP for Power-Law Graphs. 190-200
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-19 20:32 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: