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Yue Zha
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2020 – today
- 2022
- [c13]Yue Zha, Jing Li:
Revisiting PathFinder Routing Algorithm. FPGA 2022: 24-34 - 2021
- [c12]Yue Zha, Jing Li:
When application-specific ISA meets FPGAs: a multi-layer virtualization framework for heterogeneous cloud FPGAs. ASPLOS 2021: 123-134 - [c11]Yue Zha, Jing Li:
Hetero-ViTAL: A Virtualization Stack for Heterogeneous FPGA Clusters. ISCA 2021: 470-483 - 2020
- [j6]Yue Zha
, Etienne Nowak
Liquid Silicon: A Nonvolatile Fully Programmable Processing-in-Memory Processor With Monolithically Integrated ReRAM. IEEE J. Solid State Circuits 55(4): 908-919 (2020) - [j5]Jialiang Zhang, Yue Zha, Nicholas Beckwith, Bangya Liu, Jing Li:
MEG: A RISCV-based System Emulation Infrastructure for Near-data Processing Using FPGAs and High-bandwidth Memory. ACM Trans. Reconfigurable Technol. Syst. 13(4): 19:1-19:24 (2020) - [c10]Yue Zha, Jing Li:
Virtualizing FPGAs in the Cloud. ASPLOS 2020: 845-858 - [c9]Yue Zha, Jing Li:
Hyper-Ap: Enhancing Associative Processing Through A Full-Stack Optimization. ISCA 2020: 846-859
2010 – 2019
- 2019
- [c8]Jialiang Zhang, Yang Liu, Gaurav Jain, Yue Zha
MEG: A RISCV-Based System Simulation Infrastructure for Exploring Memory Optimization Using FPGAs and Hybrid Memory Cube. FCCM 2019: 145-153 - [c7]Yue Zha
Liquid Silicon: A Nonvolatile Fully Programmable Processing-In-Memory Processor with Monolithically Integrated ReRAM for Big Data/Machine Learning Applications. VLSI Circuits 2019: 206- - 2018
- [j4]Yue Zha
CMA: A Reconfigurable Complex Matching Accelerator for Wire-Speed Network Intrusion Detection. IEEE Comput. Archit. Lett. 17(1): 33-36 (2018) - [j3]Soroosh Khoram, Yue Zha
An Alternative Analytical Approach to Associative Processing. IEEE Comput. Archit. Lett. 17(2): 113-116 (2018) - [j2]Yue Zha
Specialization: A New Path Towards Low Power. J. Low Power Electron. 14(2): 195-205 (2018) - [c6]Yue Zha
Liquid Silicon-Monona: A Reconfigurable Memory-Oriented Computing Fabric with Scalable Multi-Context Support. ASPLOS 2018: 214-228 - [c5]Yue Zha
Liquid Silicon: A Data-Centric Reconfigurable Architecture Enabled by RRAM Technology. FPGA 2018: 51-60 - 2017
- [j1]Yue Zha
IMEC: A Fully Morphable In-Memory Computing Fabric Enabled by Resistive Crossbar. IEEE Comput. Archit. Lett. 16(2): 123-126 (2017) - [c4]Yue Zha, Jialiang Zhang, Zhiqiang Wei, Jing Li:
A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only). FPGA 2017: 285 - [c3]Yue Zha
RRAM-based reconfigurable in-memory computing architecture with hybrid routing. ICCAD 2017: 527-532 - [c2]Soroosh Khoram, Yue Zha
Challenges and Opportunities: From Near-memory Computing to In-memory Computing. ISPD 2017: 43-46 - 2016
- [c1]Yue Zha
Reconfigurable in-memory computing with resistive memory crossbar. ICCAD 2016: 120
Coauthor Index
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