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FPT 2012: Seoul, Korea
- 2012 International Conference on Field-Programmable Technology, FPT 2012, Seoul, Korea (South), December 10-12, 2012. IEEE 2012, ISBN 978-1-4673-2846-3
- Steven J. E. Wilton, Bradley R. Quinton, Eddie Hung:
Rapid RTL-based signal ranking for FPGA prototyping. 1-7 - Wenyi Feng:
K-way partitioning based packing for FPGA logic blocks without input bandwidth constraint. 8-15 - Qiang Liu, Jianguo Ma, Qijun Zhang:
Neural network based pre-placement wirelength estimation. 16-22 - Ju-Yueh Lee, Cheng-Ru Chang, Naifeng Jing, Juexiao Su, Shi-Jie Wen, Rick Wong, Lei He:
Heterogeneous configuration memory scrubbing for soft error mitigation in FPGAs. 23-28 - Yi Shan, Zilong Wang, Wenqiang Wang, Yuchen Hao, Yu Wang, Kuen Hung Tsoi, Wayne Luk, Huazhong Yang:
FPGA based memory efficient high resolution stereo vision system for video tolling. 29-32 - Junneng Zhang, Chao Wang, Xi Li, Peng Chen, Xiaojing Feng, Xuehai Zhou:
A task-level OoO framework for heterogeneous systems. 33-36 - Pingfan Meng, Matthew Jacobsen, Ryan Kastner
:
FPGA-GPU-CPU heterogenous architecture for real-time cardiac physiological optical mapping. 37-42 - Vincent Mirian, Paul Chow:
Managing mutex variables in a cache-coherent shared-memory system for FPGAs. 43-46 - Yutian Huan, André DeHon:
FPGA optimized packet-switched NoC using split and merge primitives. 47-52 - Chao Wang, Xi Li, Xuehai Zhou, Yajun Ha:
Parallel dataflow execution for sequential programs on reconfigurable hybrid MPSoCs. 53-56 - Abdullah Al-Dujaili, Florian Deragisch, Andrei Hagiescu, Weng-Fai Wong
Guppy: A GPU-like soft-core processor. 57-60 - Kizheppatt Vipin
A high speed open source controller for FPGA Partial Reconfiguration. 61-66 - Dongkwan Suh, Kiseok Kwon, Sukjin Kim, Soojung Ryu, Jeongwook Kim:
Design space exploration and implementation of a high performance and low area Coarse Grained Reconfigurable Processor. 67-70 - Jimmy Kwa, Tor M. Aamodt:
Small virtual channel routers on FPGAs through block RAM sharing. 71-79 - Yi-Chung Chen, Wenhua Wang, Wei Zhang
uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodology. 80-86 - Assem A. M. Bsoul, Steven J. E. Wilton:
An FPGA with power-gated switch blocks. 87-94 - Mohamed S. Abdelfattah, Vaughn Betz:
Design tradeoffs for hard and soft FPGA-based Networks-on-Chip. 95-103 - Cuong Pham-Quoc
Rule-based data communication optimization using quantitative communication profiling. 104-108 - Maciej Kurek, Wayne Luk:
Parametric reconfigurable designs with Machine Learning Optimizer. 109-112 - Benjamin Y. Brewster, Ekawat Homsirikamol, Rajesh Velegalati, Kris Gaj:
Option space exploration using distributed computing for efficient benchmarking of FPGA cryptographic modules. 113-118 - Amila Akagic
A study of adaptable co-processors for Cyclic Redundancy Check on an FPGA. 119-124 - Bernhard Jungk, Marc Stöttinger, Jan Gampe, Steffen Reith, Sorin A. Huss:
Side-channel resistant AES architecture utilizing randomized composite field representations. 125-128 - Jeremy Abramson, Pedro C. Diniz:
Resiliency-aware scheduling: Resource allocation for hardened computation on configurable devices. 129-134 - Server Kasap
FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. 135-140 - Amir Masoud Gharehbaghi
Automatic rectification of design errors in complex processors with programmable hardware. 141-146 - Tim Todman, Peter Böhm, Wayne Luk:
Verification of streaming hardware and software codesigns. 147-150 - Hui Yan Cheah, Suhaib A. Fahmy
iDEA: A DSP block based FPGA soft processor. 151-158 - Michael J. Klaiber, Lars Rockstroh, Zhe Wang, Yousef Baroud, Sven Simon:
A memory-efficient parallel single pass architecture for connected component labeling of streamed images. 159-165 - Braiden Brousseau, Jonathan Rose:
An energy-efficient, fast FPGA hardware architecture for OpenCV-Compatible object detection. 166-173 - Charles Lo, Paul Chow:
A high-performance architecture for training Viola-Jones object detectors. 174-181 - Ce Guo, Haohuan Fu, Wayne Luk:
A fully-pipelined expectation-maximization engine for Gaussian Mixture Models. 182-189 - Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang, Shaojun Wei:
Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method. 190-197 - Junying Chen, Alfred C. H. Yu
Design considerations of real-time adaptive beamformer for medical ultrasound research using FPGA and GPU. 198-205 - Janarbek Matai, Pingfan Meng, Lingjuan Wu, Brad T. Weals, Ryan Kastner
Designing a hardware in the loop wireless digital channel emulator for software defined radio. 206-214 - Abdulazim Amouri, Saman Kiamehr, Mehdi Baradaran Tahoori:
Investigation of aging effects in different implementations and structures of programmable routing resources of FPGAs. 215-219 - Yoshihiro Ichinomiya, Kohei Takano, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi:
Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration. 220-223 - Insup Shin, Donkyu Baek, Youngsoo Shin:
Introducing irregularity to routing architecture of structured ASIC for better routability. 224-228 - Jeffrey B. Goeders, Steven J. E. Wilton:
VersaPower: Power estimation for diverse FPGA architectures. 229-234 - Alexander Brant, Ameer Abdelhadi, Aaron Severance, Guy G. F. Lemieux:
Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew. 235-238 - Armin Krieg, Johannes Grinschgl, Holger Bock, Josef Haid:
Acceleration of fault attack emulation by consideration of fault propagation. 239-242 - Seunghun Jin, Sang-Heon Lee, Moo-Kyoung Chung, Yeon-Gon Cho, Soojung Ryu:
Implementation of a volume rendering on coarse-grained reconfigurable multiprocessor. 243-246 - Razvan Nane
Area constraint propagation in high level synthesis. 247-252 - Abdulhadi Shoufan
A hardware security module for quadrotor communication. 253-256 - Eduardo Peters, Ricardo P. Jasinski, Volnei A. Pedroni, Jean M. Simao:
A new hardware coprocessor for accelerating Notification-Oriented applications. 257-260 - Aaron Severance, Guy Lemieux:
VENICE: A compact vector processor for FPGA applications. 261-268 - Ying Wang, Jian Yan, Xuegong Zhou, Lingli Wang, Wayne Luk, Chenglian Peng, Jiarong Tong:
A partially reconfigurable architecture supporting hardware threads. 269-276 - Toan X. Mai, Jongeun Lee:
Software-managed automatic data sharing for Coarse-Grained Reconfigurable coprocessors. 277-284 - Liang Chen, Tulika Mitra
Graph minor approach for application mapping on CGRAs. 285-292 - Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. 293-296 - Yan Lin Aung, Siew Kei Lam, Thambipillai Srikanthan:
Area-time estimation of C-based functions for design space exploration. 297-300 - Hasan Baig
An island-style-routing compatible fault-tolerant FPGA architecture with self-repairing capabilities. 301-304 - Donald G. Bailey
Streamed high dynamic range imaging. 305-308 - Ruediger Willenberg, Paul Chow:
SimXMD: Integrated debugging of C code and hardware components. 309-312 - Hee-Seok Kim, Minwook Ahn, John A. Stratton, Wen-mei W. Hwu:
Design evaluation of OpenCL compiler framework for Coarse-Grained Reconfigurable Arrays. 313-320 - Wonsub Kim, Donghoon Yoo, Haewoo Park, Minwook Ahn:
SCC based modulo scheduling for coarse-grained reconfigurable processors. 321-328 - Changmoo Kim, Moo-Kyoung Chung, Yeon-Gon Cho, Mario Konijnenburg, Soojung Ryu, Jeongwook Kim:
ULP-SRP: Ultra low power Samsung Reconfigurable Processor for biomedical applications. 329-334 - Yongjun Park, Jason Jong Kyu Park, Scott A. Mahlke:
Efficient performance scaling of future CGRAs for mobile applications. 335-342 - Sang Woo Jun, Kermin Fleming, Michael Adler, Joel S. Emer:
ZIP-IO: Architecture for application-specific compression of Big Data. 343-351 - Guiming Wu, Xianghui Xie, Yong Dou, Junqing Sun, Dong Wu, Yuan Li:
Parallelizing sparse LU decomposition on FPGAs. 352-359 - Mohammad Reza Mohammadnia, Lesley Shannon:
Minimizing the error: A study of the implementation of an Integer Split-Radix FFT on an FPGA for medical imaging. 360-367 - Donald Donglong Chen, Gavin Xiaoxu Yao, Çetin Kaya Koç
Low complexity and hardware-friendly spectral modular multiplication. 368-375
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