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Ameer Abdelhadi
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2020 – today
- 2024
- [c23]Alberto Delmas Lascorz
, Mostafa Mahmoud
Atalanta: A Bit is Worth a "Thousand" Tensor Values. ASPLOS (2) 2024: 85-102 - [c22]Eugene Sha
Marple: Scalable Spike Sorting for Untethered Brain-Machine Interfacing. ASPLOS (2) 2024: 666-682 - [c21]Milos Nikolic, Enrique Torres-Sánchez, Jiahui Wang, Ali Hadi Zadeh, Mostafa Mahmoud, Ameer Abdelhadi, Kareem Ibrahim, Andreas Moshovos:
Schrodinger's FP Training Neural Networks with Dynamic Floating-Point Containers. MLSys 2024 - 2023
- [j4]Rahul Gulve
39 000-Subexposures/s Dual-ADC CMOS Image Sensor With Dual-Tap Coded-Exposure Pixels for Single-Shot HDR and 3-D Computational Imaging. IEEE J. Solid State Circuits 58(11): 3150-3163 (2023) - 2022
- [c20]Ameer Abdelhadi, Eugene Sha, Andreas Moshovos:
A Massive-Scale Brain Activity Decoding Chip. HCS 2022: 1-65 - [c19]Ali Hadi Zadeh
Mokey: enabling narrow fixed-point inference for out-of-the-box floating-point transformer models. ISCA 2022: 888-901 - [c18]Rahul Gulve, Navid Sarhangnejad, Gairik Dutta, Motasem Sakr, Don Nguyen, Roberto Rangel, Wenzheng Chen, Zhengfan Xia, Mian Wei, Nikita Gusev, Esther Y. H. Lin, Xiaonong Sun, Leo Hanxu, Nikola Katic, Ameer Abdelhadi, Andreas Moshovos, Kiriakos N. Kutulakos, Roman Genov:
A 39, 000 Subexposures/s CMOS Image Sensor with Dual-tap Coded-exposure Data-memory Pixel for Adaptive Single-shot Computational Imaging. VLSI Technology and Circuits 2022: 78-79 - [i2]Ali Hadi Zadeh, Mostafa Mahmoud, Ameer Abdelhadi, Andreas Moshovos:
Mokey: Enabling Narrow Fixed-Point Inference for Out-of-the-Box Floating-Point Transformer Models. CoRR abs/2203.12758 (2022) - [i1]Milos Nikolic, Enrique Torres-Sánchez, Jiahui Wang, Ali Hadi Zadeh, Mostafa Mahmoud, Ameer Abdelhadi, Andreas Moshovos:
Schrödinger's FP: Dynamic Adaptation of Floating-Point Containers for Deep Learning Training. CoRR abs/2204.13666 (2022) - 2021
- [j3]He Li
Adversarial Hardware With Functional and Topological Camouflage. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1685-1689 (2021) - [c17]Ameer M. S. Abdelhadi, He Li:
Reconfigurable Synthesizable Synchronization FIFOs. FCCM 2021: 272 - [c16]Ameer M. S. Abdelhadi, He Li:
Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs. FPL 2021: 312-318 - [c15]Ameer M. S. Abdelhadi, Eugene Sha, Ciaran Bannon, Hendrik Steenland, Andreas Moshovos:
Noema: Hardware-Efficient Template Matching for Neural Population Pattern Detection. MICRO 2021: 522-534 - [c14]Isak Edo Vivancos, Sayeh Sharify, Daniel Ly-Ma, Ameer Abdelhadi, Ciaran Bannon, Milos Nikolic, Mostafa Mahmoud, Alberto Delmas Lascorz, Gennady Pekhimenko, Andreas Moshovos:
Boveda: Building an On-Chip Deep Learning Memory Hierarchy Brick by Brick. MLSys 2021 - 2020
- [c13]Ameer M. S. Abdelhadi:
Synthesizable Synchronization FIFOs Utilizing the Asynchronous Pulse-Based Handshake Protocol. NorCAS 2020: 1-7
2010 – 2019
- 2019
- [c12]Ameer M. S. Abdelhadi, Christos-Savvas Bouganis
Accelerated Approximate Nearest Neighbors Search Through Hierarchical Product Quantization. FPT 2019: 90-98 - [c11]Ameer M. S. Abdelhadi, Lesley Shannon:
Revisiting Deep Learning Parallelism: Fine-Grained Inference Engine Utilizing Online Arithmetic. FPT 2019: 383-386 - 2018
- [c10]Ameer M. S. Abdelhadi, Guy G. F. Lemieux, Lesley Shannon:
Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories. FPL 2018: 243-250 - 2017
- [c9]Ameer M. S. Abdelhadi, Mark R. Greenstreet:
Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs. ASYNC 2017: 41-48 - 2016
- [j2]Ameer M. S. Abdelhadi, Guy G. F. Lemieux:
Modular Switched Multiported SRAM-Based Memories. ACM Trans. Reconfigurable Technol. Syst. 9(3): 22:1-22:26 (2016) - [c8]Ameer M. S. Abdelhadi, Guy G. F. Lemieux:
A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs. FCCM 2016: 140-147 - 2015
- [c7]Ameer M. S. Abdelhadi, Guy G. F. Lemieux:
Modular SRAM-Based Binary Content-Addressable Memories. FCCM 2015: 207-214 - 2014
- [c6]Ameer Abdelhadi, Guy G. F. Lemieux:
Modular multi-ported SRAM-based memories. FPGA 2014: 35-44 - [c5]Ameer M. S. Abdelhadi, Guy G. F. Lemieux:
Deep and narrow binary content-addressable memories using FPGA-based BRAMs. FPT 2014: 318-321 - 2013
- [j1]Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman:
Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks. Integr. 46(4): 382-391 (2013) - [c4]Alexander Brant, Ameer Abdelhadi, Douglas H. H. Sim, Shao Lin Tang, Michael Xi Yue, Guy G. F. Lemieux:
Safe Overclocking of Tightly Coupled CGRAs and Processor Arrays using Razor. FCCM 2013: 37-44 - 2012
- [c3]Alexander Brant, Ameer Abdelhadi, Aaron Severance, Guy G. F. Lemieux:
Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew. FPT 2012: 235-238 - 2011
- [c2]Ameer Abdelhadi, Guy G. F. Lemieux:
Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations. ReConFig 2011: 20-26 - 2010
- [c1]Ameer Abdelhadi, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman:
Timing-driven variation-aware nonuniform clock mesh synthesis. ACM Great Lakes Symposium on VLSI 2010: 15-20
Coauthor Index
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