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Douglas L. Maskell
Douglas Leslie Maskell
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- affiliation: Nanyang Technological University, Singapore
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2020 – today
- 2024
- [c71]Padmanabhan Balasubramanian
, Douglas L. Maskell:
A New Carry Look-Ahead Adder Architecture Enabling Improved Speed and Energy Efficiency. PACRIM 2024: 1-6 - [i15]Xuan Wu, Di Wang, Lijie Wen, Yubin Xiao, Chunguo Wu, Yuesong Wu, Chaoyu Yu, Douglas L. Maskell, You Zhou:
Neural Combinatorial Optimization Algorithms for Solving Vehicle Routing Problems: A Comprehensive Survey with Perspectives. CoRR abs/2406.00415 (2024) - [i14]Padmanabhan Balasubramanian, Douglas L. Maskell:
Fast Bipartitioned Hybrid Adder Utilizing Carry Select and Carry Lookahead Logic. CoRR abs/2412.01764 (2024) - 2023
- [j41]Xiangwei Li
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation. ACM Trans. Reconfigurable Technol. Syst. 16(1): 9:1-9:24 (2023) - [i13]P. Balasubramanian, Douglas L. Maskell:
Fault-Tolerant Design Approach Based on Approximate Computing. CoRR abs/2311.00328 (2023) - 2022
- [j40]Padmanabhan Balasubramanian
Approximator: A Software Tool for Automatic Generation of Approximate Arithmetic Circuits. Comput. 11(1): 11 (2022) - [j39]Abhishek Kumar Jain
Coarse Grained FPGA Overlay for Rapid Just-In-Time Accelerator Compilation. IEEE Trans. Parallel Distributed Syst. 33(6): 1478-1490 (2022) - 2021
- [j38]Padmanabhan Balasubramanian
An Approximate Adder With a Near-Normal Error Distribution: Design, Error Analysis and Practical Application. IEEE Access 9: 4518-4530 (2021) - [c70]Padmanabhan Balasubramanian, Raunaq Nayar
An Approximate Adder with Reduced Error and Optimized Design Metrics. APCCAS 2021: 21-24 - [c69]Raunaq Nayar
Image Compression using Approximate Addition. TENCON 2021: 1-6 - [i12]P. Balasubramanian, Raunaq Nayar, Douglas L. Maskell:
Gate-Level Static Approximate Adders. CoRR abs/2112.09320 (2021) - 2020
- [c68]Tao Luo
Energy Efficient In-memory Integer Multiplication Based on Racetrack Memory. ICDCS 2020: 1409-1414 - [c67]Xiangwei Li
High Throughput Accelerator Interface Framework for a Linear Time-Multiplexed FPGA Overlay. ISCAS 2020: 1-5 - [c66]Raunaq Nayar
Hardware Optimized Approximate Adder with Normal Error Distribution. ISVLSI 2020: 84-89 - [i11]P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis:
Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications. CoRR abs/2008.05685 (2020)
2010 – 2019
- 2019
- [j37]Jaytrilok Choudhary
Generalized Majority Voter Design Method for N-Modular Redundant Systems Used in Mission- and Safety-Critical Applications. Comput. 8(1): 10 (2019) - [j36]Xiangwei Li
Time-Multiplexed FPGA Overlay Architectures: A Survey. ACM Trans. Design Autom. Electr. Syst. 24(5): 54:1-54:19 (2019) - [c65]P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis:
Area Optimized Quasi Delay Insensitive Majority Voter for TMR Applications. EECS 2019: 37-44 - [i10]P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis:
Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results. CoRR abs/1901.09315 (2019) - [i9]P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis:
Majority and Minority Voted Redundancy for Safety-Critical Applications. CoRR abs/1901.09316 (2019) - [i8]P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis:
Speed and Energy Optimised Quasi-Delay-Insensitive Block Carry Lookahead Adder. CoRR abs/1903.09433 (2019) - [i7]P. Balasubramanian, Douglas L. Maskell:
Indicating Asynchronous Array Multipliers. CoRR abs/1905.05904 (2019) - [i6]P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis:
Indicating Asynchronous Multipliers. CoRR abs/1905.11231 (2019) - 2018
- [j35]P. Balasubramanian
A Self-Healing Redundancy Scheme for Mission/Safety-Critical Applications. IEEE Access 6: 69640-69649 (2018) - [c64]Xiangwei Li
A time-multiplexed FPGA overlay with linear interconnect. DATE 2018: 1075-1080 - [c63]P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis:
Indicating Asynchronous Multipliers. EECS 2018: 547-553 - [c62]P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis:
Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results. MWSCAS 2018: 587-590 - [c61]P. Balasubramanian, Douglas L. Maskell, Nikos E. Mastorakis:
Majority and Minority Voted Redundancy for Safety-Critical Applications. MWSCAS 2018: 1102-1105 - [c60]P. Balasubramanian, Douglas L. Maskell, Krishnamachar Prasad:
A System Health Indicator for the Distributed Minority and Majority Voting Based Redundancy Scheme. TENCON 2018: 530-535 - [c59]P. Balasubramanian, Douglas L. Maskell:
Hardware Efficient Approximate Adder Design. TENCON 2018: 806-810 - 2017
- [j34]Tao Luo
A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency. IEEE Trans. Circuits Syst. II Express Briefs 64-II(1): 71-75 (2017) - [c58]Tao Luo
A novel two-stage modular multiplier based on racetrack memory for asymmetric cryptography. ICCAD 2017: 276-282 - [c57]P. Balasubramanian, Cuong Dang
Approximate quasi-delay-insensitive asynchronous adders: Design and analysis. MWSCAS 2017: 1196-1199 - [i5]Abhishek Kumar Jain
Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays. CoRR abs/1705.02730 (2017) - [i4]P. Balasubramanian, Cuong Dang, Douglas L. Maskell, K. Prasad:
Asynchronous Early Output Section-Carry Based Carry Lookahead Adder with Alias Carry Logic. CoRR abs/1710.05470 (2017) - [i3]P. Balasubramanian, Cuong Dang, Douglas L. Maskell, K. Prasad:
Approximate Ripple Carry and Carry Lookahead Adders - A Comparative Analysis. CoRR abs/1710.05474 (2017) - 2016
- [c56]Tao Luo
A racetrack memory based in-memory booth multiplier for cryptography application. ASP-DAC 2016: 286-291 - [c55]Abhishek Kumar Jain
Are Coarse-Grained Overlays Ready for General Purpose Application Acceleration on FPGAs? DASC/PiCom/DataCom/CyberSciTech 2016: 586-593 - [c54]Abhishek Kumar Jain, Douglas L. Maskell, Suhaib A. Fahmy:
Throughput oriented FPGA overlays using DSP blocks. DATE 2016: 1628-1633 - [c53]Abhishek Kumar Jain
DeCO: A DSP Block Based FPGA Accelerator Overlay with Low Overhead Interconnect. FCCM 2016: 1-8 - [i2]Xiangwei Li, Abhishek Kumar Jain
An Area-Efficient FPGA Overlay using DSP Block based Time-multiplexed Functional Units. CoRR abs/1606.06460 (2016) - 2015
- [j33]P. Balasubramanian, Douglas L. Maskell:
A distributed minority and majority voting based redundancy scheme. Microelectron. Reliab. 55(9-10): 1373-1378 (2015) - [j32]Abhishek Kumar Jain, Xiangwei Li
Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq. SIGARCH Comput. Archit. News 43(4): 28-33 (2015) - [j31]Xinan Zhang
An Improved Robust Field-Weakeaning Algorithm for Direct-Torque-Controlled Synchronous-Reluctance-Motor Drives. IEEE Trans. Ind. Electron. 62(5): 3255-3264 (2015) - [c52]Abhishek Kumar Jain
Efficient Overlay Architecture Based on DSP Blocks. FCCM 2015: 25-28 - [c51]Lian Lian Jiang, Douglas L. Maskell:
Automatic fault detection and diagnosis for photovoltaic systems using combined artificial neural network and analytical based methods. IJCNN 2015: 1-8 - [c50]Weigui Jair Zhou, Douglas Leslie Maskell, Chai Quek
FIE-FCMAC: A novel fuzzy cerebellum model articulation controller (FCMAC) using fuzzy interpolation and extrapolation technique. IJCNN 2015: 1-8 - 2014
- [j30]Hui Yan Cheah, Fredrik Brosser, Suhaib A. Fahmy
The iDEA DSP Block-Based Soft Processor for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 7(3): 19:1-19:23 (2014) - [j29]Abhishek Kumar Jain
Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform. J. Signal Process. Syst. 77(1-2): 61-76 (2014) - [c49]Lian Lian Jiang, Douglas L. Maskell:
A uniform implementation scheme for evolutionary optimization algorithms and the experimental implementation of an ACO based MPPT for PV systems under partial shading. CIASG 2014: 109-116 - [c48]D. R. Nayanasiri
Soft-switching single inductor current-fed push-pull converter for PV applications. IECON 2014: 5589-5594 - [c47]Dulika R. Nayanasiri
HFL micro inverter with front-end diode clamped multi-level inverter and half-wave cycloconverter. ISIE 2014: 503-508 - 2013
- [j28]Yupeng Chen, Bertil Schmidt
A hybrid short read mapping accelerator. BMC Bioinform. 14: 67 (2013) - [j27]Sunita Chandrasekaran, Shilpa Shanbagh, Ramkumar Jayaraman, Douglas L. Maskell, Hui Yan Cheah:
C2FPGA - A dependency-timing graph design methodology. J. Parallel Distributed Comput. 73(11): 1417-1429 (2013) - [j26]Yupeng Chen, Bertil Schmidt
Reconfigurable Accelerator for the Word-Matching Stage of BLASTN. IEEE Trans. Very Large Scale Integr. Syst. 21(4): 659-669 (2013) - [c46]Khoa Dang Pham, Abhishek Kumar Jain
Microkernel hypervisor for a hybrid ARM-FPGA platform. ASAP 2013: 219-226 - [c45]D. R. Nayanasiri
Current-controlled resonant circuit based photovoltaic micro-inverter with half- wave cycloconverter. IAS 2013: 1-6 - [c44]Lian Lian Jiang, D. R. Nayanasiri
A simple and efficient hybrid maximum power point tracking method for PV systems under partially shaded condition. IECON 2013: 1513-1518 - [c43]D. R. Nayanasiri
High-frequency-link micro-inverter with front-end current-fed half-bridge boost converter and half-wave cycloconverter. IECON 2013: 6987-6992 - [c42]Weigui Jair Zhou, Douglas Leslie Maskell, Chai Quek
Fuzzy interpolation and extrapolation using shift ratio and overall weight measurement based on areas of fuzzy sets. UKCI 2013: 46-53 - 2012
- [j25]Yongchao Liu
CUSHAW: a CUDA compatible short read aligner to large genomes based on the Burrows-Wheeler transform. Bioinform. 28(14): 1830-1837 (2012) - [j24]Jin Cui, Douglas L. Maskell:
A Fast High-Level Event-Driven Thermal Estimator for Dynamic Thermal Aware Scheduling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(6): 904-917 (2012) - [c41]Hui Yan Cheah, Suhaib A. Fahmy
A lean FPGA soft processor built using a DSP block. FPGA 2012: 237-240 - [c40]Yupeng Chen, Bertil Schmidt
Accelerating short read mapping on an FPGA (abstract only). FPGA 2012: 265 - [c39]Yupeng Chen, Bertil Schmidt
An FPGA aligner for short read mapping. FPL 2012: 511-514 - [c38]Hui Yan Cheah, Suhaib A. Fahmy
iDEA: A DSP block based FPGA soft processor. FPT 2012: 151-158 - [c37]Lian Lian Jiang, Douglas L. Maskell, Jagdish Chandra Patra
A flann-based controller for maximum power point tracking in PV systems under rapidly changing conditions. ICASSP 2012: 2141-2144 - [c36]Lian Lian Jiang, Douglas L. Maskell, Jagdish Chandra Patra
Chebyshev Functional Link Neural Network-based modeling and experimental verification for photovoltaic arrays. IJCNN 2012: 1-8 - [c35]Bertil Schmidt, Douglas L. Maskell:
Fourth Workshop on using Emerging Parallel Architectures. ICCS 2012: 1867-1869 - 2011
- [j23]Lakshmi Kuttippurathu
CompleteMOTIFs: DNA motif discovery platform for transcription factor binding experiments. Bioinform. 27(5): 715-717 (2011) - [j22]Yongchao Liu
DecGPU: distributed error correction on massively parallel graphics processing units using CUDA and MPI. BMC Bioinform. 12: 85 (2011) - [j21]Yongchao Liu
Parallelized short read assembly of large genomes using de Bruijn graphs. BMC Bioinform. 12: 354 (2011) - [j20]Chai Quek
A Novel Fuzzy Associative Memory Architecture for Stock Market Prediction and Trading. Int. J. Fuzzy Syst. Appl. 1(1): 61-78 (2011) - [c34]Yongchao Liu
An Ultrafast Scalable Many-Core Motif Discovery Algorithm for Multiple GPUs. IPDPS Workshops 2011: 428-434 - [c33]Ramkumar Jayaraman, Handi Kartadihardja, Douglas L. Maskell:
Performance-Power Design Space Exploration in a Hybrid Computing Platform Suitable for Mobile Applications. ISED 2011: 140-145 - [c32]Jagdish Chandra Patra
Estimation of external quantum efficiency for multi-junction solar cells under influence of charged particles using artificial neural networks. SMC 2011: 465-470 - [c31]Bertil Schmidt, Douglas L. Maskell:
Third Workshop on using Emerging Parallel Architectures. ICCS 2011: 1964-1966 - 2010
- [j19]Yongchao Liu
MSAProbs: multiple sequence alignment based on pair hidden Markov models and partition function posterior probabilities. Bioinform. 26(16): 1958-1964 (2010) - [j18]Achutavarrier Prasad Vinod
An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth. Integr. 43(1): 124-135 (2010) - [j17]Yongchao Liu
CUDA-MEME: Accelerating motif discovery in biological sequences using CUDA-enabled graphics processing units. Pattern Recognit. Lett. 31(14): 2170-2177 (2010) - [j16]Ghee Ming Goh, Chai Quek
EpiList II: Closing the Loop in the Development of Generic Cognitive Skills. IEEE Trans. Syst. Man Cybern. Part A 40(4): 676-685 (2010) - [c30]Jin Cui, Douglas L. Maskell:
High level event driven thermal estimation for thermal aware task allocation and scheduling. ASP-DAC 2010: 793-798 - [c29]Sunita Chandrasekaran, Shilpa Shanbagh, Douglas L. Maskell:
A dependency graph based methodology for parallelizing HLL applications on FPGA (abstract only). FPGA 2010: 286 - [c28]Bertil Schmidt, Douglas L. Maskell:
Second Workshop on using Emerging Parallel Architectures. ICCS 2010: 1015-1017
2000 – 2009
- 2009
- [j15]Timothy F. Oliver, Bertil Schmidt
High Speed Biological Sequence Analysis With Hidden Markov Models on Reconfigurable Platforms. IEEE Trans. Inf. Technol. Biomed. 13(5): 740-746 (2009) - [c27]Yupeng Chen, Bertil Schmidt
A Reconfigurable Bloom Filter Architecture for BLASTN. ARCS 2009: 40-49 - [c26]Yongchao Liu
MSA-CUDA: Multiple Sequence Alignment on Graphics Processing Units with CUDA. ASAP 2009: 121-128 - [c25]Jin Cui, Douglas L. Maskell:
Dynamic thermal-aware scheduling on chip multiprocessor for soft real-time system. ACM Great Lakes Symposium on VLSI 2009: 393-396 - [c24]Bertil Schmidt, Douglas L. Maskell:
Workshop on Using Emerging Parallel Architectures for Computational Science. ICCS (1) 2009: 861-863 - [c23]Yongchao Liu
Parallel reconstruction of neighbor-joining trees for large multiple sequence alignments using CUDA. IPDPS 2009: 1-8 - 2008
- [j14]Yi Wang
A unified architecture for a public key cryptographic coprocessor. J. Syst. Archit. 54(10): 1004-1016 (2008) - [c22]Douglas L. Maskell, A. Prasad Vinod
Efficient multiplierless channel filters for multi-standard SDR. CIT 2008: 237-242 - [c21]Douglas L. Maskell, Achutavarrier Prasad Vinod
Multiplierless multi-standard SDR channel filters. MMSP 2008: 815-819 - 2007
- [j13]Timothy F. Oliver, Douglas L. Maskell:
Prerouted FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System. EURASIP J. Embed. Syst. 2007 (2007) - [j12]Douglas L. Maskell:
Design of efficient multiplierless FIR filters. IET Circuits Devices Syst. 1(2): 175-180 (2007) - [j11]Xiaoyong Chen, Douglas L. Maskell:
Supporting multiple-input, multiple-output custom functions in configurable processors. J. Syst. Archit. 53(5-6): 263-271 (2007) - [j10]Xiaoyong Chen, Douglas L. Maskell, Yang Sun:
Fast Identification of Custom Instructions for Extensible Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 359-368 (2007) - [c20]Alvin Cai, Chai Quek
Type-2 GA-TSK fuzzy neural network. IEEE Congress on Evolutionary Computation 2007: 1578-1585 - [c19]Ian McLoughlin
An Embedded Systems graduate education for Singapore. ICPADS 2007: 1-5 - [c18]Yan Lin Aung, Douglas L. Maskell, Timothy F. Oliver, Bertil Schmidt
C-Based Design Methodology for FPGA Implementation of ClustalW MSA. PRIB 2007: 11-18 - 2006
- [j9]Timothy F. Oliver, Bertil Schmidt
High-speed Multiple Sequence Alignment on a reconfigurable platform. Int. J. Bioinform. Res. Appl. 2(4): 394-406 (2006) - [j8]Jussipekka Leiwo, Lam-for Kwok
A technique for expressing IT security objectives. Inf. Softw. Technol. 48(7): 532-539 (2006) - [j7]Douglas L. Maskell, Graham S. Woods:
Adaptive subsample delay estimation using windowed correlation. IEEE Trans. Circuits Syst. II Express Briefs 53-II(6): 478-482 (2006) - [c17]Xiaoyong Chen, Douglas L. Maskell, Yang Sun:
Automatic Identification of Custom Functions for Embedded Processors with MIMO Extensions. APCCAS 2006: 1156-1159 - [c16]Yi Wang
Unified Signed-Digit Number Adder for RSA and ECC Public-key Cryptosystems. APCCAS 2006: 1655-1658 - [c15]Xiaoyong Chen, Douglas L. Maskell:
M2E: A Multiple-Input, Multiple-Output Function Extension for RISC-Based Extensible Processors. ARCS 2006: 191-201 - [c14]Chee H. Lee, Chai Quek, Douglas L. Maskell:
A Brain Inspired Fuzzy Neuro-predictor for Bank Failure Analysis. IEEE Congress on Evolutionary Computation 2006: 2163-2170 - [c13]Zaiyi Guo, Chai Quek, Douglas L. Maskell:
FCMAC-AARS: A Novel FNN Architecture for Stock Market Prediction and Trading. IEEE Congress on Evolutionary Computation 2006: 2375-2381 - [c12]Timothy F. Oliver, Douglas L. Maskell:
Execution Objects for Dynamically Reconfigurable FPGA Systems. FPL 2006: 1-4 - [c11]K. S. Tham, Douglas L. Maskell:
Software-Oriented Approach to Hardware-Software Co-Simulation for FPGA-Based Risc Extensible Processor. FPL 2006: 1-6 - [c10]Timothy F. Oliver, Bertil Schmidt
Accelerating the Viterbi Algorithm for Profile Hidden Markov Models Using Reconfigurable Hardware. International Conference on Computational Science (1) 2006: 522-529 - [c9]Douglas L. Maskell, Jussipekka Leiwo, Jagdish Chandra Patra:
The design of multiplierless FIR filters with a minimum adder step and reduced hardware complexity. ISCAS 2006 - [i1]Douglas L. Maskell, Timothy F. Oliver:
Pre-Routed FPGA Cores for Rapid System Construction in a Dynamic Reconfigurable System. Dynamically Reconfigurable Architectures 2006 - 2005
- [j6]Timothy F. Oliver, Bertil Schmidt
Using reconfigurable hardware to accelerate multiple sequence alignment with ClustalW. Bioinform. 21(16): 3431-3432 (2005) - [j5]Douglas L. Maskell, Graham S. Woods:
Adaptive subsample delay estimation using a modified quadrature phase detector. IEEE Trans. Circuits Syst. II Express Briefs 52-II(10): 669-674 (2005) - [j4]Timothy F. Oliver, Bertil Schmidt
Reconfigurable architectures for bio-sequence database scanning on FPGAs. IEEE Trans. Circuits Syst. II Express Briefs 52-II(12): 851-855 (2005) - [c8]K. S. Tham, Douglas L. Maskell:
Software-Oriented System-Level Simulation for Design Space Exploration of Reconfigurable Architectures. Asia-Pacific Computer Systems Architecture Conference 2005: 391-404 - [c7]Jacop Yanto, Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell:
Biological Sequence Analysis with Hidden Markov Models on an FPGA. Asia-Pacific Computer Systems Architecture Conference 2005: 429-439 - [c6]Timothy F. Oliver, Bertil Schmidt
Hyper customized processors for bio-sequence database scanning on FPGAs. FPGA 2005: 229-237 - [c5]Timothy F. Oliver, Douglas L. Maskell:
An FPGA Model for Developing Dynamic Circuit Computing. FPT 2005: 281-282 - [c4]Timothy F. Oliver, Bertil Schmidt
Multiple Sequence Alignment on an FPGA. ICPADS (2) 2005: 326-330 - [c3]Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell, Achutavarrier Prasad Vinod
A reconfigurable architecture for scanning biosequence databases. ISCAS (5) 2005: 4799-4802 - 2004
- [c2]Douglas L. Maskell, Graham S. Woods, Andrew Kerans:
A hardware efficient implementation of an adaptive subsample delay estimator. ISCAS (3) 2004: 317-320 - 2003
- [c1]Timothy F. Oliver, Douglas L. Maskell:
Towards Run-Time Re-Configurable Techniques for Real-Time Embedded Applications. Engineering of Reconfigurable Systems and Algorithms 2003: 141-146 - 2002
- [j3]Douglas L. Maskell, Graham S. Woods:
The discrete-time quadrature subsample estimation of delay. IEEE Trans. Instrum. Meas. 51(1): 133-137 (2002) - 2000
- [j2]Douglas L. Maskell, Graham S. Woods:
A frequency modulated envelope delay FSCW radar for multiple-target applications. IEEE Trans. Instrum. Meas. 49(4): 710-715 (2000)
1990 – 1999
- 1999
- [j1]Douglas L. Maskell, Graham S. Woods:
The estimation of subsample time delay of arrival in the discrete-time measurement of phase delay. IEEE Trans. Instrum. Meas. 48(6): 1227-1231 (1999)
Coauthor Index
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