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DFT 2011: Vancouver, BC, Canada
- 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1713-0
- Jinghang Liang, Jie Han, Fabrizio Lombardi:
On the Reliable Performance of Sequential Adders for Soft Computing. 3-10 - Costas Argyrides, Ronaldo Rodrigues Ferreira, Carlos Arthur Lang Lisbôa, Luigi Carro
:
Decimal Hamming: A Software-Implemented Technique to Cope with Soft Errors. 11-17 - Daniele Rossi
Impact of Aging Phenomena on Soft Error Susceptibility. 18-24 - Gabriel L. Nazar, Luigi Carro
An Area Effective Parity-Based Fault Detection Technique for FPGAs. 27-33 - Cristiana Bolchini
A Reliability-Aware Partitioner for Multi-FPGA Platforms. 34-40 - Mario Schölzel:
Fine-Grained Software-Based Self-Repair of VLIW Processors. 41-49 - Zahra Lak, Nicola Nicolici:
A New Algorithm for Post-Silicon Clock Measurement and Tuning. 53-59 - Hao Chen, Jie Han, Fabrizio Lombardi:
A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS Circuits. 60-67 - Seyab Khan, Nor Zaidi Haron, Said Hamdioui, Francky Catthoor:
NBTI Monitoring and Design for Reliability in Nanoscale Circuits. 68-76 - Md. Muwyid U. Khan, Pritish Narayanan, Priyamvada Vijayakumar, Israel Koren, C. Mani Krishna, Csaba Andras Moritz:
Biased Voting for Improved Yield in Nanoscale Fabrics. 79-85 - Behnam Ghavami, Mohsen Raji
CNT-count Failure Characteristics of Carbon Nanotube FETs under Process Variations. 86-92 - Luca Amati, Cristiana Bolchini
Optimal Test Set Selection for Fault Diagnosis Improvement. 93-99 - Daniel B. Limbrick
Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits. 103-111 - Ahmed Awad, Abdallatif S. Abu-Issa, Said Hamdioui:
Reducing Test Power for Embedded Memories. 112-119 - Mohammad Hossein Neishaburi, Zeljko Zilic:
Hierarchical Embedded Logic Analyzer for Accurate Root-Cause Analysis. 120-128 - Chandra Babu Dara, Spyros Tragoudas, Themistoklis Haniotakis:
A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate. 131-138 - Nivesh Rai, Hamidreza Hashempour, Yizi Xing, Bram Kruseman, Said Hamdioui:
A Schematic-Based Extraction Methodology for Dislocation Defects in Analog/Mixed-Signal Devices. 139-145 - Masoud Zamani, Hossein Pedram, Fabrizio Lombardi:
Templated-Based Asynchronous Design for Testable and Fail-Safe Operation. 146-152 - Dan Alexandrescu, Enrico Costenaro, Michael Nicolaidis:
A Practical Approach to Single Event Transients Analysis for Highly Complex Designs. 155-163 - Uljana Reinsalu, Jaan Raik
Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations. 164-170 - Cristiana Bolchini
An Application-Level Dependability Analysis Framework for Embedded Systems. 171-178 - Glenn H. Chapman, Bonnie L. Gray, Vijay K. Jain:
Creating Defect Tolerance in Microfluidic Capacitive/Photonic Biosensors. 181-189 - Joon-Sung Yang, Rudrajit Datta:
Efficient Function Mapping in Nanoscale Crossbar Architecture. 190-196 - Jongho Seol, Noh-Jin Park, K. M. George, Nohpill Park:
Modeling Yield of Self-Healing Carbon Nanotubes/Silicon-Nanowire FET-based Nanoarray. 197-205 - Javier Carretero, Jaume Abella
Control-Flow Recovery Validation Using Microarchitectural Invariants. 209-216 - Xun Tang, Wu-Tung Cheng, Ruifeng Guo
Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence Tree. 217-225 - Paolo Bernardi
On the Modeling of Gate Delay Faults by Means of Transition Delay Faults. 226-232 - Vijay K. Jain, Glenn H. Chapman:
Enhanced Defect Tolerance through Matrixed Deployment of Intelligent Sensors for the Smart Power Grid. 235-242 - Erik MacLean, Vijay K. Jain:
A Power Transmission Line Fault Distance Estimation VLSI Chip: Design and Defect Tolerance. 243-251 - Daniele Giaffreda, Martin Omaña, Daniele Rossi
Model for Thermal Behavior of Shaded Photovoltaic Cells under Hot-Spot Condition. 252-258 - Sreenivas Gangadhar, Spyros Tragoudas:
A Probabilistic Approach to Diagnose SETs. 261-267 - Masayoshi Yoshimura, Yusuke Akamine, Yusuke Matsunaga:
A Soft Error Tolerance Estimation Method for Sequential Circuits. 268-276 - Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer, Alireza Nojeh:
A Unified Error Control Coding Scheme to Enhance the Reliability of a Hybrid Wireless Network-on-Chip. 277-285 - Masato Inoue, Haruhiko Kaneko:
Deletion/Insertion/Reversal Error Correcting Codes for Bit-Patterned Media Recording. 286-293 - Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. 294-301 - Rodrigo Possamai Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre:
A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies. 302-308 - Nachiket Rajderkar, Marco Ottavi
On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS. 309-315 - Tobias Koal, Daniel Scheit, Mario Schölzel, Heinrich Theodor Vierhaus:
On the Feasibility of Built-In Self Repair for Logic Circuits. 316-324 - Mehran Mozaffari Kermani
Reliable Hardware Architectures for the Third-Round SHA-3 Finalist Grostl Benchmarked on FPGA Platform. 325-331 - Rudrajit Datta, Nur A. Touba:
X-Stacking - A Method for Reducing Control Data for Output Compaction. 332-338 - Rance Rodrigues, Israel Koren, Sandip Kundu:
An Architecture to Enable Life Cycle Testing in CMPs. 341-348 - Paolo Roberto Grassi, Mariagiovanna Sami, Ettore Speziale, Michele Tartara:
Analyzing the Sensitivity to Faults of Synchronization Primitives. 349-355 - Shuai Wang:
Characterizing System-Level Vulnerability for Instruction Caches against Soft Errors. 356-363 - Rudrajit Datta, Nur A. Touba:
Generating Burst-Error Correcting Codes from Orthogonal Latin Square Codes - A Graph Theoretic Approach. 367-373 - Muhammad Aamir Khan, Hans G. Kerkhoff:
SoC Mixed-Signal Dependability Enhancement: A Strategy from Design to End-of-Life. 374-381 - Sven Eisenhardt, Anja Küster, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel:
Spatial and Temporal Data Path Remapping for Fault-Tolerant Coarse-Grained Reconfigurable Architectures. 382-388 - Jorge Luis Lagos-Benites
An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems. 391-398 - Mohammad Hossein Neishaburi, Zeljko Zilic:
Debug Aware AXI-based Network Interface. 399-407 - Glenn H. Chapman, Jenny Leung, Ana I. L. Namburete
Predicting Pixel Defect Rates Based on Image Sensor Parameters. 408-416 - Geunho Cho, Fabrizio Lombardi:
On the Delay Analysis of Defective CNTFETs with Undeposited CNTs. 419-425 - Noor M. Nayeem, Jacqueline E. Rice:
Online Fault Detection in Reversible Logic. 426-434 - Masoud Zamani, Mehdi Baradaran Tahoori:
Online Missing/Repeated Gate Faults Detection in Reversible Circuits. 435-442 - Mohammad Hossein Neishaburi, Zeljko Zilic:
A Fault Tolerant Hierarchical Network on Chip Router Architecture. 445-453 - Khalid Latif, Amir-Mohammad Rahmani, Ethiopia Nigussie, Hannu Tenhunen
A Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-Chip. 454-462 - Masashi Imai, Tomohiro Yoneda:
Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories. 463-471 - Hiroshi Kutami, Yusuke Fukushima, Masaru Fukushi, Ikuko Eguchi Yairi
Route-Aware Task Mapping Method for Fault-Tolerant 2D-Mesh Network-on-Chips. 472-480
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