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19th Asian Test Symposium 2010: Shanghai, China
- Proceedings of the 19th IEEE Asian Test Symposium, ATS 2010, 1-4 December 2010, Shanghai, China. IEEE Computer Society 2010, ISBN 978-0-7695-4248-5
- Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto:
Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level. 3-8 - Hyun Woo Choi, Abhijit Chatterjee:
Jitter Characterization of Pseudo-random Bit Sequences Using Incoherent Sub-sampling. 9-14 - Min Li, Michael S. Hsiao:
FSimGP^2: An Efficient Fault Simulator with GPGPU. 15-20 - Shiyi Xu, Peng Xu:
A Quasi-best Random Testing. 21-26 - Yang Zhao, Krishnendu Chakrabarty
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Testing of Low-Cost Digital Microfluidic Biochips with Non-regular Array Layouts. 27-32 - Dipak Kumar Kole, Hafizur Rahaman
Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits. 33-38 - Melanie Elm, Michael A. Kochte, Hans-Joachim Wunderlich:
On Determining the Real Output Xs by SAT-Based Reasoning. 39-44 - Xiang Fu, Huawei Li, Xiaowei Li:
On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing. 45-48 - M. H. Haghbayan, Sara Karamati, Fatemeh Javaheri, Zainalabedin Navabi:
Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment. 53-56 - Saparya Krishnamoorthy, Michael S. Hsiao, Loganathan Lingappan:
Tackling the Path Explosion Problem in Symbolic Execution-Driven Test Generation for Programs. 59-64 - Peng Xu, Shiyi Xu:
A Reliability Model for Object-Oriented Software. 65-70 - Pan Liu, Huaikou Miao:
A New Approach to Generating High Quality Test Cases. 71-76 - Jungang Lou
A Study on Software Reliability Prediction Based on Transduction Inference. 77-80 - Bowen Chen, Haihua Shen, Wenhui Zhang:
Formula-Oriented Compositional Minimization in Model Checking. 81-84 - Fabian Hopsch, Bernd Becker
Variation-Aware Fault Modeling. 87-93 - Xun Tang, Wu-Tung Cheng, Ruifeng Guo
Diagnosis of Multiple Physical Defects Using Logic Fault Models. 94-99 - Paolo Rech
A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. 100-105 - Dan Zhu, Tun Li, Sikun Li:
On Soft Error Immunity of Sequential Circuits. 106-110 - Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman
Testing of Digital Microfluidic Biochips Using Improved Eulerization Techniques and the Chinese Postman Problem. 111-116 - Song Jin, Yinhe Han, Huawei Li, Xiaowei Li:
P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework. 117-120 - Hyunjin Kim, Jacob A. Abraham:
A Low Cost Built-In Self-Test Circuit for High-Speed Source Synchronous Memory Interfaces. 123-128 - Wei-Cheng Lien
A Complete Logic BIST Technology with No Storage Requirement. 129-134 - Iftekhar Ibne Basith, Nabeeh Kandalaft, Rashid Rashidzadeh:
Built-In Self-Test for Capacitive MEMS Using a Charge Control Technique. 135-140 - Xrysovalantis Kavousianos, Krishnendu Chakrabarty
Defect Coverage-Driven Window-Based Test Compression. 141-146 - Hiroshi Yokoyama, Hideo Tamamoto, Kewal K. Saluja:
Controlling Peak Power Consumption for Scan Based Multiple Weighted Random BIST. 147-152 - Piyanart Kongtim, Taweesak Reungpeerakul:
Parallel LFSR Reseeding with Selection Register for Mixed-Mode BIST. 153-158 - Mudassar Majeed, Daniel Ahlstrom, Urban Ingelsson, Gunnar Carlsson, Erik Larsson
Efficient Embedding of Deterministic Test Data. 159-162 - Masashi Ishikawa, Hiroyuki Yotsuyanagi, Masaki Hashizume:
Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter Code. 163-166 - Jianjun Yu, Fa Foster Dai:
On-chip Jitter Measurement Using Vernier Ring Time-to-Digital Converter. 167-170 - Nader Alawadhi, Ozgur Sinanoglu
Pattern Encodability Enhancements for Test Stimulus Decompressors. 173-178 - Thomas Rabenalt, Michael Richter, Michael Gössel:
High Performance Compaction for Test Responses with Many Unknowns. 179-184 - Yizi Xing, Liquan Fang:
Design-for-Test of Digitally-Assisted Analog IPs for Automotive SoCs. 185-191 - Jing Ye, Xiaolin Zhang, Yu Hu, Xiaowei Li:
Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method. 192-197 - Nicolas Hebert, Pascal Benoit, Gilles Sassatelli, Lionel Torres:
D-Scale: A Scalable System-Level Dependable Method for MPSoCs. 198-205 - Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara:
Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits. 206-211 - Samah Mohamed Saeed, Ozgur Sinanoglu
XOR-Based Response Compactor Adaptive to X-Density Variation. 212-217 - Nikhil P. Rahagude, Maheshwar Chandrasekar, Michael S. Hsiao:
DFT + DFD: An Integrated Method for Design for Testability and Diagnosability. 218-223 - Yan Zheng, Hong Wang, Shiyuan Yang, Chen Jiang, Feiyu Gao:
Accelerating Strategy for Functional Test of NoC Communication Fabric. 224-227 - Tsung-Chu Huang, Kuei-Yeh Lu, Yen-Chieh Huang:
HYPERA: High-Yield Performance-Efficient Redundancy Analysis. 231-236 - Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer:
A Comprehensive System-on-Chip Logic Diagnosis. 237-242 - Xiao Liu, Qiang Xu
On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation. 243-248 - Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta:
HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC. 249-254 - Wu-Tung Cheng, Yu Huang:
Enhance Profiling-Based Scan Chain Diagnosis by Pattern Masking. 255-260 - Chih-Yun Pai, Katherine Shu-Min Li:
Maximal Resilience for Reliability and Yield Enhancement in Interconnect Structure. 261-266 - Joonsung Park, Jae Wook Lee, Jaeyong Chung
At-speed Test of High-Speed DUT Using Built-Off Test Interface. 269-274 - Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee:
Rapid Radio Frequency Amplitude and Phase Distortion Measurement Using Amplitude Modulated Stimulus. 277-282 - Shyam Kumar Devarakond, Shreyas Sen, Vishwanath Natarajan, Aritra Banerjee, Hyun Woo Choi, Ganesh Srinivasan, Abhijit Chatterjee:
Digitally Assisted Concurrent Built-In Tuning of RF Systems Using Hamming Distance Proportional Signatures. 283-288 - Xiaoqin Sheng, Hans G. Kerkhoff:
The Test Ability of an Adaptive Pulse Wave for ADC Testing. 289-294 - Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir:
Bayesian Fault Diagnosis of RF Circuits Using Nonparametric Density Estimation. 295-298 - Wei Zhao, Junxia Ma, Mohammad Tehranipoor, Sreejit Chakravarty:
Power-Safe Application of Transition Delay Fault Patterns Considering Current Limit during Wafer Test. 301-306 - Sandeep Kumar Goel, Krishnendu Chakrabarty
Circuit Topology-Based Test Pattern Generation for Small-Delay Defects. 307-312 - Tomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara:
Seed Ordering and Selection for High Quality Delay Test. 313-318 - Zijian He, Tao Lv, Huawei Li, Xiaowei Li:
An Efficient Algorithm for Finding a Universal Set of Testable Long Paths. 319-324 - Xi Qian, Adit D. Singh:
Distinguishing Resistive Small Delay Defects from Random Parameter Variations. 325-330 - Ke Peng, Mahmut Yilmaz, Krishnendu Chakrabarty
A Noise-Aware Hybrid Method for SDD Pattern Grading and Selection. 331-336 - Tung-Hua Yeh, Sying-Jyan Wang
Thermal Safe High Level Test Synthesis for Hierarchical Testability. 337-342 - Kentaroh Katoh, Kazuteru Namba, Hideo Ito:
A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit. 343-348 - Irith Pomeranz, Sudhakar M. Reddy:
On Bias in Transition Coverage of Test Sets for Path Delay Faults. 349-352 - Xijiang Lin, Janusz Rajski:
Adaptive Low Shift Power Test Pattern Generator for Logic BIST. 355-360 - Chun-Yong Liang, Meng-Fan Wu, Jiun-Lang Huang:
Power Supply Noise Reduction in Broadcast-Based Compression Environment for At-speed Scan Testing. 361-366 - Amit Mishra, Nidhi Sinha, Satdev, Virendra Singh, Sreejit Chakravarty, Adit D. Singh:
Modified Scan Flip-Flop for Low Power Testing. 367-370 - Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara:
Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power. 371-374 - Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
A Test Integration Methodology for 3D Integrated Circuits. 377-382 - Jhih-Wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu
Performance Characterization of TSV in 3D IC via Sensitivity Analysis. 389-394 - Nima Aghaee
Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation. 395-398 - S. Krishna Kumar, S. Kaundinya, Santanu Chattopadhyay:
Particle Swarm Optimization Based Scheme for Low Power March Sequence Generation for Memory Testing. 401-406 - NurQamarina MohdNoor, Azilah Saparon
New Microcode's Generation Technique for Programmable Memory Built-In Self Test. 407-412 - Ying Zhang, Huawei Li, Xiaowei Li:
Software-Based Self-Testing of Processors Using Expanded Instructions. 415-420 - Hongxia Fang, Zhiyuan Wang, Xinli Gu, Krishnendu Chakrabarty
Mimicking of Functional State Space with Structural Tests for the Diagnosis of Board-Level Functional Failures. 421-428 - Zhaobo Zhang, Zhanglei Wang, Xinli Gu, Krishnendu Chakrabarty
Optimization and Selection of Diagnosis-Oriented Fault-Insertion Points for System Test. 429-432 - Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker, Erik Jan Marinissen
Test Cost Analysis for 3D Die-to-Wafer Stacking. 435-441 - Neha Goel, Michael S. Hsiao, Naren Ramakrishnan
Mining Complex Boolean Expressions for Sequential Equivalence Checking. 442-447 - Qi Guo, Tianshi Chen, Haihua Shen, Yunji Chen
On-the-Fly Reduction of Stimuli for Functional Verification. 448-454 - Farrokh Ghani Zadegan
Test Time Analysis for IEEE P1687. 455-460
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