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Zhiqiang You
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2020 – today
- 2024
- [c14]Zhijian Peng, Peng Liu, Lian Yao, Zhiqiang You, Bosheng Liu, Yang Yi, Jigang Wu:
A Complementary Resistive Switch-Based Balanced Ternary Logic. ITC-Asia 2024: 1-6 - [c13]Minghe Zhang, Guanglun Huang, Guoliang Ji, Zhiqiang You, Qiang Wu, Jianyu Cao:
A Scan Slice Reordering Algorithm Based on Minimizing Entropy to Enhance Test Data Compression Efficiency. ITC-Asia 2024: 1-6 - [c12]Zhiwei Zhong, Zhiqiang You, Peng Liu:
A Dynamic Weight Quantization-Based Fault-tolerant Training Method for Ternary Memristive Neural Networks. ITC-Asia 2024: 1-6 - 2023
- [c11]Jing Yang, Zhiqiang You, Zhiwei Zhong, Peng Liu, Langqi Mei, Shenguang Huang:
DTTR: Detecting Text with Transformers. ICASSP 2023: 1-5 - 2021
- [j24]Peng Liu
, Zhiqiang You
Fault Modeling and Efficient Testing of Memristor-Based Memory. IEEE Trans. Circuits Syst. I Regul. Pap. 68(11): 4444-4455 (2021) - [j23]Lian Yao
Integrating Two Logics Into One Crossbar Array for Logic Gate Design. IEEE Trans. Circuits Syst. II Express Briefs 68(8): 2987-2991 (2021) - [j22]Peng Liu
Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory. IEEE Trans. Emerg. Top. Comput. 9(2): 745-758 (2021) - 2020
- [j21]Pavlo Melnyk
A high-performance CNN method for offline handwritten Chinese character recognition and visualization. Soft Comput. 24(11): 7977-7987 (2020)
2010 – 2019
- 2019
- [j20]Wei Liang
Efficient data packet transmission algorithm for IPV6 mobile vehicle network based on fast switching model with time difference. Future Gener. Comput. Syst. 100: 132-143 (2019) - [c10]Minghe Zhang, Jishun Kuang, Jing Huang, Zhiqiang You:
A Pseudo-Random Transform Decomposition Method for Improving the Coding Compression Ratio of Test Data. HPCC/SmartCity/DSS 2019: 1611-1618 - 2018
- [j19]Liubao Deng, Zhiqiang You, Yuefen Chen:
Optimistic value model of multidimensional uncertain optimal control with jump. Eur. J. Control 39: 1-7 (2018) - [j18]Yan Chen, Zhiqiang You, Yingjie Zhang, Jishun Kuang, Jing Zhang:
A novel memristor-based restricted Boltzmann machine for contrastive divergence. IEICE Electron. Express 15(2): 20171062 (2018) - [c9]Peng Liu, Jigang Wu, Zhiqiang You, Michael Elimu, Weizheng Wang, Shuo Cai:
Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory. ATS 2018: 25-29 - [i2]Pavlo Melnyk, Zhiqiang You, Keqin Li:
A High-Performance CNN Method for Offline Handwritten Chinese Character Recognition and Visualization. CoRR abs/1812.11489 (2018) - 2016
- [j17]Liao Wu, Jishun Kuang, Zhiqiang You, Peng Liu, Shuo Cai:
A parallel-SSHI rectifier for ultra-low-voltage piezoelectric vibration energy harvesting. IEICE Electron. Express 13(17): 20160539 (2016) - 2015
- [j16]Bosheng Liu
A signal degradation reduction method for memristor ratioed logic (MRL) gates. IEICE Electron. Express 12(8): 20150062 (2015) - [j15]Peng Liu, Zhiqiang You, Jishun Kuang, Zhipeng Hu, Weizheng Wang:
Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm. IEICE Electron. Express 12(23): 20150839 (2015) - [j14]Tieqiao Liu, Jishun Kuang, Shuo Cai, Zhiqiang You:
An efficient small-delay faults simulator based on critical path tracing. Int. J. Circuit Theory Appl. 43(8): 1015-1023 (2015) - [c8]Jishun Kuang, Liang Zhang, Zhiqiang You, Yingbo Zhou:
Improve the compression ratios for code-based test vector compressions by decomposing. ETS 2015: 1-6 - 2014
- [j13]Weiwei Wang, Zhiqiang You, Peng Liu, Jishun Kuang:
An adaptive neural network A/D converter based on CMOS/memristor hybrid design. IEICE Electron. Express 11(24): 20141012 (2014) - [i1]Zhiqiang You, Xiao-Pu Han, Linyuan Lü, Chi Ho Yeung:
Empirical studies on the network of social groups: the case of Tencent QQ. CoRR abs/1408.5558 (2014) - 2013
- [j12]Bosheng Liu
Comparator and half adder design using complementary resistive switches crossbar. IEICE Electron. Express 10(13): 20130369 (2013) - [j11]Aobo Pan, Yaping Lin, Wenjie Che
A comprehensive metering scheme for intellectual property protection during both after-sale and evaluation periods of IC design. IEICE Electron. Express 10(19): 20130649 (2013) - 2012
- [j10]Zhiqiang You, Weizheng Wang, Peng Liu, Jishun Kuang, Zheng Qin:
A scan disabling-based BAST scheme for test cost and test power reduction. IEICE Electron. Express 9(2): 111-116 (2012) - [j9]Weizheng Wang, Jishun Kuang, Peng Liu, Xin Peng, Zhiqiang You:
Switching activity reduction for scan-based BIST using weighted scan input data. IEICE Electron. Express 9(10): 874-880 (2012) - [j8]Huaiyu Xu, Jihui Xu, Zhiqiang You, Wenqi Peng, Kunlin Zhang, Jinfeng Xu:
Thermal Simulation of Traction System for High-Speed Train Based on Heat Accumulation. J. Comput. 7(4): 1034-1040 (2012) - [j7]Weizheng Wang, Jishun Kuang, Zhiqiang You:
Achieving low capture and shift power in linear decompressor-based test compression environment. Microelectron. J. 43(2): 134-140 (2012) - [j6]Ling Zhang, Jishun Kuang, Zhiqiang You:
Virtual scan chains reordering using a RAM-based module for high test compression. Microelectron. J. 43(11): 869-872 (2012) - 2011
- [j5]Ling Zhang, Jishun Kuang, Zhiqiang You:
Test Data Compression Using Selective Sparse Storage. J. Electron. Test. 27(4): 565-577 (2011) - [j4]Zhiqiang You, Weizheng Wang, Zhiping Dou, Peng Liu, Jishun Kuang:
A scan disabling-based BAST scheme for test cost reduction. IEICE Electron. Express 8(16): 1367-1373 (2011) - [j3]Ling Zhang, Jishun Kuang, Zhiqiang You:
Test data compression using interval broadcast scan for embedded cores. Microelectron. J. 42(11): 1313-1319 (2011) - 2010
- [c7]Zhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara:
Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power. Asian Test Symposium 2010: 371-374 - [c6]Ling Zhang, Jishun Kuang, Zhiqiang You:
Test Data Compression Using Four-Coded and Sparse Storage for Testing Embedded Core. ICA3PP (2) 2010: 434-443 - [c5]Dayu Shi, Huaiyu Xu, Ruidan Su
A GEO-Related IOT Applications Platform Based on Google Map. ICEBE 2010: 380-384
2000 – 2009
- 2008
- [c4]Jishun Kuang, Ouyang Xiong, Zhiqiang You:
A Novel BIST Scheme Using Test Vectors Applied by Circuit-under-Test Itself. ATS 2008: 75-80 - [c3]Gui Dai, Zhiqiang You, Jishun Kuang, Jiedi Huang:
DCScan: A Power-Aware Scan Testing Architecture. ATS 2008: 348-455 - [c2]Yong-sheng Cheng, Zhiqiang You, Jishun Kuang:
Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction. DELTA 2008: 308-313 - 2006
- [j2]Zhiqiang You, Tsuyoshi Iwagaki, Michiko Inoue, Hideo Fujiwara:
A Low Power Deterministic Test Using Scan Chain Disable Technique. IEICE Trans. Inf. Syst. 89-D(6): 1931-1939 (2006) - 2005
- [j1]Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara:
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths. IEICE Trans. Inf. Syst. 88-D(8): 1940-1947 (2005) - 2004
- [c1]Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara:
Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths. Asian Test Symposium 2004: 32-39
Coauthor Index
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last updated on 2024-10-16 20:31 CEST by the dblp team
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