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D. M. H. Walker
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- affiliation: Texas A&M University, College Station, Texas, USA
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2020 – today
- 2023
- [j17]Avijit Chakraborty
, Duncan M. Hank Walker
Topological Heuristics for Scan Test Overhead Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 2043-2054 (2023) - 2020
- [c68]Avijit Chakraborty, D. M. H. Walker:
Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits. DFT 2020: 1-4
2010 – 2019
- 2017
- [c67]Prasenjit Biswas, D. M. H. Walker:
Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra. VLSID 2017: 141-146 - 2015
- [j16]Yukun Gao, Tengteng Zhang, Punj Pokharel, Swati Chakraborty, D. M. H. Walker:
Pseudo Functional Path Delay Test through Embedded Memories. J. Electron. Test. 31(1): 35-42 (2015) - [j15]Tengteng Zhang, Yukun Gao, D. M. H. Walker:
Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise. J. Electron. Test. 31(1): 99-106 (2015) - [c66]Tengteng Zhang, D. M. H. Walker:
Impact of test compression on power supply noise control. DFTS 2015: 161-166 - [c65]Avijit Chakraborty, D. M. H. Walker:
Optimizing VMIN of ROM Arrays Without Loss of Noise Margin. ACM Great Lakes Symposium on VLSI 2015: 397-402 - [c64]Swati Chakraborty, Duncan M. Hank Walker:
At-Speed Path Delay Test. NATW 2015: 39-42 - 2014
- [c63]Tengteng Zhang, Yukun Gao, D. M. H. Walker:
Pattern Generation for Post-Silicon Timing Validation Considering Power Supply Noise. NATW 2014: 61-64 - [c62]Yukun Gao, Tengteng Zhang, Swati Chakraborty, D. M. H. Walker:
Delay Test of Embedded Memories. NATW 2014: 65-68 - [c61]Kun Bian, D. M. H. Walker, Sunil P. Khatri:
Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation. VLSID 2014: 50-55 - [c60]Tengteng Zhang, Duncan M. Hank Walker:
Improved power supply noise control for pseudo functional test. VTS 2014: 1-6 - [p1]Duncan M. Hank Walker:
K Longest Paths. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 23-48 - 2013
- [c59]Kun Bian, D. M. H. Walker, Sunil P. Khatri, Shayak Lahiri:
Mixed structural-functional path delay test generation and compaction. DFTS 2013: 7-12 - [c58]Tengteng Zhang, Duncan M. Hank Walker:
Power supply noise control in pseudo functional test. VTS 2013: 1-6 - 2012
- [c57]Dibakar Gope, D. M. H. Walker:
Maximizing crosstalk-induced slowdown during path delay test. ICCD 2012: 159-166 - 2011
- [c56]Zhongwei Jiang, Zheng Wang, Jing Wang, D. M. H. Walker:
Levelized low cost delay test compaction considering IR-drop induced power supply noise. VTS 2011: 52-57
2000 – 2009
- 2009
- [c55]D. M. H. Walker:
Challenges in Delay Testing of Integrated Circuits. DFT 2009: 81-82 - [c54]Zheng Wang, Duncan M. Hank Walker:
Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric. VTS 2009: 59-64 - 2008
- [j14]Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri, D. M. H. Walker:
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integr. 41(3): 399-412 (2008) - [c53]Zheng Wang, D. M. H. Walker:
Dynamic Compaction for High Quality Delay Test. VTS 2008: 243-248 - 2007
- [j13]Jing Wang, Duncan M. Hank Walker, Xiang Lu, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul J. A. M. van de Wiel, Stefan Eichenberger:
Modeling Power Supply Noise in Delay Testing. IEEE Des. Test Comput. 24(3): 226-234 (2007) - 2006
- [j12]Sagar S. Sabade, D. M. H. Walker:
Estimation of fault-free leakage current using wafer-level spatial information. IEEE Trans. Very Large Scale Integr. Syst. 14(1): 91-94 (2006) - [c52]Wangqi Qiu, D. M. H. Walker, Neil Simpson, Divya Reddy, Anthony Moore:
Comparison of Delay Tests on Silicon. ITC 2006: 1-10 - [c51]Jing Wang, D. M. H. Walker, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul van de Wiel, Stefan Eichenberger:
Power Supply Noise in Delay Testing. ITC 2006: 1-10 - [c50]Hyun Sung Kim, D. M. H. Walker:
Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in {VLSI} Circuits. MTV 2006: 76-82 - 2005
- [j11]Sagar S. Sabade, Duncan M. Hank Walker:
IC Outlier Identification Using Multiple Test Metrics. IEEE Des. Test Comput. 22(6): 586-595 (2005) - [j10]Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi:
Longest-path selection for delay test under process variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12): 1924-1929 (2005) - [c49]Lei Wu, D. M. H. Walker:
A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits. DFT 2005: 178-186 - [c48]Jing Wang, Ziding Yue, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker:
A vector-based approach for power supply noise analysis in test compaction. ITC 2005: 10 - [c47]Bin Xue, D. M. H. Walker:
IDDQ test using built-in current sensing of supply line voltage drop. ITC 2005: 10 - [c46]Eunjae Jung, Duncan M. Hank Walker:
Reliable energy efficient routing in wireless sensor networks. MASS 2005 - [c45]Bin Xue, D. M. H. Walker:
Is IDDQ Test of Microprocessors Feasible? MTV 2005: 63-69 - [c44]Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker:
Static Compaction of Delay Tests Considering Power Supply Noise. VTS 2005: 235-240 - 2004
- [j9]Sagar S. Sabade, D. M. H. Walker:
IDDQ data analysis using neighbor current ratios. J. Syst. Archit. 50(5): 287-294 (2004) - [j8]Sagar S. Sabade, D. M. H. Walker:
IDDX-based test methods: A survey. ACM Trans. Design Autom. Electr. Syst. 9(2): 159-198 (2004) - [c43]Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi:
Longest path selection for delay test under process variation. ASP-DAC 2004: 98-103 - [c42]Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi:
PARADE: PARAmetric Delay Evaluation under Process Variation. ISQED 2004: 276-280 - [c41]Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran:
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. ITC 2004: 223-231 - [c40]Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi:
A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. MTV 2004: 97-102 - [c39]Sagar S. Sabade, D. M. H. Walker:
Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests. VLSI Design 2004: 889-894 - [c38]Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi:
A Statistical Fault Coverage Metric for Realistic Path Delay Faults. VTS 2004: 37-42 - [c37]Sagar S. Sabade, D. M. H. Walker:
On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set. VTS 2004: 65-72 - 2003
- [j7]Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker:
A circuit level fault model for resistive bridges. ACM Trans. Design Autom. Electr. Syst. 8(4): 546-559 (2003) - [c36]Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi:
CodSim -- A Combined Delay Fault Simulator. DFT 2003: 79- - [c35]Sagar S. Sabade, D. M. H. Walker:
CROWNE: Current Ratio Outliers with Neighbor Estimator. DFT 2003: 132-139 - [c34]Abhijit Prasad, D. M. H. Walker:
Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors. DFT 2003: 140- - [c33]Wangqi Qiu, D. M. H. Walker:
An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit. ITC 2003: 592-601 - [c32]Wangqi Qiu, D. M. H. Walker:
Testing the Path Delay Faults of ISCAS85 Circuit c6288. MTV 2003: 19- - [c31]Sagar S. Sabade, D. M. H. Walker:
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification. VLSI Design 2003: 361- - [c30]Sagar S. Sabade, D. M. H. Walker:
Use of Multiple IDDQ Test Metrics for Outlier Identification. VTS 2003: 31-38 - [c29]Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker:
A Circuit Level Fault Model for Resistive Opens and Bridges. VTS 2003: 379-384 - 2002
- [j6]Sagar S. Sabade, D. M. H. Walker:
IDDQ Test: Will It Survive the DSM Challenge? IEEE Des. Test Comput. 19(5): 8-16 (2002) - [c28]Sagar S. Sabade, D. M. H. Walker:
Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis. DFT 2002: 381-389 - [c27]Sagar S. Sabade, D. M. H. Walker:
Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. ASP-DAC/VLSI Design 2002: 755-760 - [c26]Sagar S. Sabade, D. M. H. Walker:
Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction. VTS 2002: 81-86 - 2001
- [c25]Wanlin Cao, D. M. H. Walker, Rajarshi Mukherjee:
An efficient solution to the storage correspondence problem for large sequential circuits. ASP-DAC 2001: 181-186 - [c24]Sagar S. Sabade, D. M. H. Walker:
Improved wafer-level spatial analysis for I_DDQ limit setting. ITC 2001: 82-91 - [c23]Hoki Kim, D. M. H. Walker, David Colby:
A practical built-in current sensor for I_DDQ testing. ITC 2001: 405-414 - [c22]Zoran Stanojevic, D. M. H. Walker:
FedEx - a fast bridging fault extractor. ITC 2001: 696-703 - 2000
- [c21]Zoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler:
Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. ITC 2000: 729-738 - [c20]Byungwoo Choi, D. M. H. Walker:
Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. VTS 2000: 49-54 - [c19]Chul Young Lee, D. M. H. Walker:
PROBE: A PPSFP Simulator for Resistive Bridging Faults. VTS 2000: 105-112
1990 – 1999
- 1999
- [c18]Lan Zhao, D. M. H. Walker, Fabrizio Lombardi:
IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs. Asian Test Symposium 1999: 375- - [c17]Vijay R. Sar-Dessai, D. M. H. Walker:
Resistive bridge fault modeling, simulation and test generation. ITC 1999: 596-605 - [c16]D. M. H. Walker:
Design for Yield and Reliability is MORE Important Than DFT. ITC 1999: 1146 - [c15]Debashis Nayak, D. M. H. Walker:
Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits. VTS 1999: 70-79 - 1998
- [j5]Lan Zhao, D. M. H. Walker, Fabrizio Lombardi:
IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays. IEEE Trans. Computers 47(10): 1136-1152 (1998) - [c14]Vijay R. Sar-Dessai, D. M. H. Walker:
Accurate Fault Modeling and Fault Simulation of Resistive Bridges. DFT 1998: 102-107 - [c13]Lan Zhao, D. M. H. Walker, Fabrizio Lombardi:
Bridging Fault Detection in FPGA Interconnects Using IDDQ. FPGA 1998: 95-104 - [c12]Lan Zhao, D. M. H. Walker, Fabrizio Lombardi:
Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ. ITC 1998: 1037-1046 - 1996
- [c11]Dinesh D. Gaitonde, Wojciech Maly, D. M. H. Walker:
Fatal Fault Probability Prediction for Array Based Designs. DFT 1996: 30-38 - [c10]G. M. Luong, D. M. H. Walker:
Test Generation for Global Delay Faults. ITC 1996: 433-442 - [c9]Yuyun Liao, D. M. H. Walker:
Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages. ITC 1996: 767-775 - [c8]Hari Balachandran, D. M. H. Walker:
Improvement of SRAM-based failure analysis using calibrated Iddq testing. VTS 1996: 130-137 - [c7]Yuyun Liao, D. M. H. Walker:
Optimal voltage testing for physically-based faults. VTS 1996: 344-353 - 1995
- [c6]Dinesh D. Gaitonde, D. M. H. Walker, Wojciech Maly:
Accurate yield estimation of circuits with redundancy. DFT 1995: 155-163 - [c5]V. Ramakrishnan, D. M. H. Walker:
IC Performance Prediction System. ITC 1995: 336-344 - [c4]Young-Jun Kwon, D. M. H. Walker:
Yiel Learning via Functional Test Data. ITC 1995: 626-635 - 1994
- [j4]Martin D. Giles, Duane S. Boning, Goodwin R. Chin, Walter C. Dietrich Jr., Michael S. Karasick, Mark E. Law, Purnendu K. Mozumder, Lee R. Nackman, V. T. Rajan, Duncan M. Hank Walker, Robert H. Wang, Alexander S. Wong:
Semiconductor wafer representation for TCAD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(1): 82-95 (1994) - 1993
- [j3]D. M. H. Walker, Chris S. Kellen, David M. Svoboda, Andrzej J. Strojwas:
The CDB/HCDB semiconductor wafer representation server. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(2): 283-295 (1993) - [c3]Dinesh D. Gaitonde, Duncan M. Hank Walker:
Test quality and yield analysis using the DEFAM defect to fault mapper. ICCAD 1993: 202-205 - [c2]Dinesh D. Gaitonde, Jitendra Khare, D. M. H. Walker, Wojciech P. Maly:
Estimation of reject ratio in testing of combinatorial circuits. VTS 1993: 319-325 - 1991
- [c1]D. M. H. Walker, Chris S. Kellen, Andrzej J. Strojwas:
A Semiconductor Wafer Representation Database and Its Use in the PREDITOR Process Editor and Statistical Simulator. DAC 1991: 579-584 - 1990
- [j2]Duncan M. Hank Walker, D. S. Nydick:
DVLASIC: catastrophic fault yield simulation in a distributed processing environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(6): 655-664 (1990)
1980 – 1989
- 1986
- [j1]D. M. H. Walker, Stephen W. Director:
VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(4): 541-556 (1986)
Coauthor Index
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