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Jose Manuel Mendias
José M. Mendías
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- affiliation: Universidad Complutense de Madrid, Spain
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2020 – today
- 2024
- [j20]Borja Morcillo
, Daniel Báscones
Parametric Pipelined k-Means Implementation for Hyperspectral Processing on Spacecraft Embedded FPGA. IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens. 17: 15927-15941 (2024)
2010 – 2019
- 2015
- [j19]Miguel Peón Quirós, Alexandros Bartzas, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris:
Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems. ACM Trans. Embed. Comput. Syst. 14(2): 37:1-37:30 (2015) - 2014
- [j18]Alberto A. Del Barrio
Improving circuit performance with multispeculative additive trees in high-level synthesis. Microelectron. J. 45(11): 1470-1479 (2014) - 2013
- [j17]Alberto A. Del Barrio
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths. Integr. 46(2): 119-130 (2013) - [c48]Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, Jose Manuel Mendias, María C. Molina:
Multispeculative additive trees in high-level synthesis. DATE 2013: 188-193 - 2012
- [j16]Alberto A. Del Barrio
Multispeculative Addition Applied to Datapath Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1817-1830 (2012) - 2011
- [j15]Alberto A. Del Barrio
A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 350-363 (2011) - [c47]Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, José M. Mendías, Román Hermida:
Power optimization in heterogenous datapaths. DATE 2011: 1400-1405 - 2010
- [j14]Alexandros Bartzas, Miguel Peón Quirós, Christophe Poucet, Christos Baloukas, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias:
Software metadata: Systematic characterization of the memory behaviour of dynamic applications. J. Syst. Softw. 83(6): 1051-1075 (2010) - [c46]Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Román Hermida, Seda Ogrenci Memik:
Using Speculative Functional Units in high level synthesis. DATE 2010: 1779-1784
2000 – 2009
- 2009
- [j13]María C. Molina, Rafael Ruiz-Sautua, Alberto A. Del Barrio
Subword Switching Activity Minimization to Optimize Dynamic Power Consumption. IEEE Des. Test Comput. 26(4): 68-77 (2009) - [j12]María C. Molina, Rafael Ruiz-Sautua, Pedro Garcia-Repetto, José M. Mendías:
Performance-driven scheduling of behavioural specifications. Integr. 42(3): 294-303 (2009) - [j11]Alexandros Bartzas, Miguel Peón Quirós, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias:
Direct memory access usage optimization in network applications for reduced memory latency and energy consumption. J. Embed. Comput. 3(3): 241-254 (2009) - 2008
- [c45]Alexandros Bartzas, Miguel Peón Quirós, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias:
Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information. ASP-DAC 2008: 434-439 - [c44]Alberto A. Del Barrio
Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis. DSD 2008: 267-273 - [c43]Alberto A. Del Barrio
Applying speculation techniques to implement functional units. ICCD 2008: 74-80 - 2007
- [j10]Rafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias:
Exploiting Bit-Level Delay Calculations to Soften Read-After-Write Dependences in Behavioral Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1589-1601 (2007) - [j9]David Atienza
HW-SW emulation framework for temperature-aware design in MPSoCs. ACM Trans. Design Autom. Electr. Syst. 12(3): 26:1-26:26 (2007) - [c42]María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida
Area optimization of multi-cycle operators in high-level synthesis. DATE 2007: 449-454 - [c41]Salvatore Carta, Andrea Acquaviva, Pablo García Del Valle, David Atienza, Giovanni De Micheli, Fernando Rincón
Multi-processor operating system emulation framework with thermal feedback for systems-on-chip. ACM Great Lakes Symposium on VLSI 2007: 311-316 - [c40]Miguel Peón Quirós, Alexandros Bartzas, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris
Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption. PATMOS 2007: 373-383 - [i1]Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida:
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. CoRR abs/0710.4801 (2007) - 2006
- [j8]David Atienza
Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems. Integr. 39(2): 113-130 (2006) - [j7]María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida
Bitwise scheduling to balance the computational cost of behavioral specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1): 31-46 (2006) - [j6]David Atienza
Systematic dynamic memory management design methodology for reduced memory footprint. ACM Trans. Design Autom. Electr. Syst. 11(2): 465-489 (2006) - [c39]David Atienza, Pablo García Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip. DAC 2006: 618-623 - [c38]Stylianos Mamagkakis, David Atienza, Christophe Poucet, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias:
Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems. DATE 2006: 874-875 - [c37]Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida:
Pre-synthesis optimization of multiplications to improve circuit performance. DATE 2006: 1306-1311 - [c36]Alexandros Bartzas, Miguel Peón Quirós, Stylianos Mamagkakis, David Atienza
Systematic design flow for dynamic data management in visual texture decoder of MPEG-4. ISCAS 2006 - [c35]Pablo García Del Valle, David Atienza, Ivan Magan, Javier Garcia Flores, Esther Andres Perez, Jose Manuel Mendias, Luca Benini
A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework. VLSI-SoC 2006: 140-145 - 2005
- [j5]Marc Leeman, David Atienza, Geert Deconinck
Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications. J. VLSI Signal Process. 40(3): 383-396 (2005) - [c34]Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida:
Arrival time aware scheduling to minimize clock cycle length. ASP-DAC 2005: 1018-1021 - [c33]Nicolas Genko, David Atienza
A Complete Network-On-Chip Emulation Framework. DATE 2005: 246-251 - [c32]Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. DATE 2005: 1252-1257 - [c31]Rafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias, Román Hermida
Performance-driven read-after-write dependencies softening in high-level synthesis. ICCAD 2005: 7-12 - [c30]Nicolas Genko, David Atienza
A novel approach for network on chip emulation. ISCAS (3) 2005: 2365-2368 - [c29]J. B. Pérez-Ramas, David Atienza, Miguel Peón Quirós, Ivan Magan, Jose Manuel Mendias, Román Hermida:
Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs. PARCO 2005: 769-776 - [c28]José Manuel Velasco, David Atienza, Katzalin Olcoz, Francky Catthoor, Francisco Tirado, Jose Manuel Mendias:
Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems. PATMOS 2005: 69-78 - [c27]Stylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, José M. Mendías, Antonios Thanailakis:
Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications. WWIC 2005: 354-364 - 2004
- [j4]Edgar G. Daylight, David Atienza
Memory-access-aware data structure transformations for embedded software with dynamic data accesses. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 269-280 (2004) - [c26]José Manuel Velasco, David Atienza, Francky Catthoor, Francisco Tirado
Garbage Collector Refinement for New Dynamic Multimedia Applications on Embedded Systems. Interaction between Compilers and Computer Architectures 2004: 25-32 - [c25]Francesco Poletti, Paul Marchal, David Atienza, Luca Benini, Francky Catthoor, Jose Manuel Mendias:
An integrated hardware/software approach for run-time scratchpad management. DAC 2004: 238-243 - [c24]David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris
Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications. DATE 2004: 532-537 - [c23]María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
Behavioural Bitwise Scheduling Based on Computational Effort Balancing. DATE 2004: 684-685 - [c22]David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris:
Reducing memory accesses with a system-level design methodology in customized dynamic memory management. ESTIMedia 2004: 93-98 - [c21]David Atienza, Marc Leeman, Francky Catthoor, Geert Deconinck
Fast prototyping and refinement of complex dynamic data types in multimedia applications for consumer embedded devices. ICME 2004: 803-806 - [c20]María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida
Behavioural Scheduling to Balance the Bit-Level Computational Effort. ISVLSI 2004: 99-104 - [c19]David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris:
Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems. PATMOS 2004: 510-520 - [c18]Stylianos Mamagkakis, Alexandros Mpartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias, Antonios Thanailakis:
Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology. WWIC 2004: 26-37 - 2003
- [j3]María C. Molina, José M. Mendías, Román Hermida
Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources. J. Syst. Archit. 49(12-15): 505-519 (2003) - [c17]María C. Molina, José M. Mendías, Román Hermida:
High-Level Allocation to Minimize Internal Hardware Wastage. DATE 2003: 10264-10269 - [c16]Marc Leeman, David Atienza, Francky Catthoor, Vincenzo De Florio, Geert Deconinck
Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level. PATMOS 2003: 289-298 - [c15]María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida:
Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. PATMOS 2003: 617-627 - 2002
- [j2]José M. Mendías, Román Hermida, Olga Peñalba:
A study about the efficiency of formal high-level synthesis applied to verification. Integr. 31(2): 101-131 (2002) - [j1]Olga Peñalba, José M. Mendías, Román Hermida
A global approach to improve conditional hardware reuse in high-level synthesis. J. Syst. Archit. 47(12): 959-975 (2002) - [c14]María C. Molina, José M. Mendías, Román Hermida:
High-level synthesis of multiple-precision circuitsindependent of data-objects length. DAC 2002: 612-615 - [c13]María C. Molina, José M. Mendías, Román Hermida
Multiple-Precision Circuits Allocation Independent of Data-Objects Length. DATE 2002: 909-913 - [c12]Olga Peñalba, José M. Mendías, Román Hermida
Maximizing Conditonal Reuse by Pre-Synthesis Transformations. DATE 2002: 1097 - [c11]Aitor Ibarra
Optimization of Equational Specifications Using Genetic Techniques. DSD 2002: 252-258 - [c10]José M. Mendías, Román Hermida
Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis. DSD 2002: 308-315 - [c9]Olga Peñalba, José M. Mendías, Román Hermida
Source Code Transformation to Improve Conditional Hardware Reuse. DSD 2002: 324-331 - [c8]María C. Molina, José M. Mendías, Román Hermida
Bit-Level Allocation of Multiple-Precision Specifications. DSD 2002: 385-392 - [c7]Aitor Ibarra, Juan Lanchares, Jose Manuel Mendias, José Ignacio Hidalgo, Román Hermida:
Transformation of Equational Specification by Means of Genetic Programming. EuroGP 2002: 248-257 - [c6]María C. Molina, José M. Mendías, Román Hermida
Bit-level scheduling of heterogeneous behavioural specifications. ICCAD 2002: 602-608 - 2000
- [c5]Olga Peñalba, José M. Mendías, María C. Molina:
Execution Condition Analysis in High Level Synthesis: A Unified Approach. ISSS 2000: 73-78
1990 – 1999
- 1999
- [c4]Olga Peñalba, José M. Mendías, Román Hermida
A Unified Algorithm for Mutual Exclusiveness Identification. EUROMICRO 1999: 1504-1510 - 1998
- [c3]José M. Mendías, Román Hermida
Correct High-Level Synthesis: a Formal Perspective. DATE 1998: 977-978 - 1997
- [c2]José M. Mendías, Román Hermida, Milagros Fernández:
Formal Techniques for Hardware Allocation. VLSI Design 1997: 161-165 - 1996
- [c1]José M. Mendías, Román Hermida
Algebraic Support for Transformational Hardware Allocation. ED&TC 1996: 601
Coauthor Index
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