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Marko Aleksic
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2010 – 2019
- 2018
- [c10]Marko Aleksic, Vanja Jovanovic:
Non-physical Painting Restoration in Improved Reality. VRTCH 2018: 206-214 - 2015
- [j7]Reza Navid, E-Hung Chen, Masum Hossain, Brian S. Leibowitz, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble:
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology. IEEE J. Solid State Circuits 50(4): 814-827 (2015) - 2014
- [c9]Marko Aleksic:
A 3.2-GHz 1.3-mW ILO phase rotator for burst-mode mobile memory I/O in 28-nm low-leakage CMOS. ESSCIRC 2014: 451-454 - [c8]E-Hung Chen, Masum Hossain, Brian S. Leibowitz, Reza Navid, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble:
A 40-Gb/s serial link transceiver in 28-nm CMOS technology. VLSIC 2014: 1-2 - 2010
- [j6]Brian S. Leibowitz, Robert Palmer, John Poulton, Yohan Frans, Simon Li, John M. Wilson, Michael Bucher, Andrew M. Fuller, John G. Eyles, Marko Aleksic, Trey Greer, Nhat Nguyen:
A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling. IEEE J. Solid State Circuits 45(4): 889-898 (2010)
2000 – 2009
- 2009
- [j5]Haechang Lee, Kun-Yung Ken Chang, Jung-Hoon Chun, Ting Wu, Yohan Frans, Brian S. Leibowitz, Nhat Nguyen, T. J. Chin, Kambiz Kaviani, Jie Shen, Xudong Shi, Wendemagegnehu T. Beyene, Simon Li, Reza Navid, Marko Aleksic, Fred S. Lee, Fredy Quan, Jared Zerbe, Rich Perego, Fariborz Assaderaghi:
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface. IEEE J. Solid State Circuits 44(4): 1235-1247 (2009) - [j4]Marko Aleksic, Peyman Razaghi, Wei Yu:
Capacity of a Class of Modulo-Sum Relay Channels. IEEE Trans. Inf. Theory 55(3): 921-930 (2009) - 2008
- [j3]Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija:
Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(10): 3038-3049 (2008) - 2007
- [c7]Marko Aleksic, Peyman Razaghi, Wei Yu:
Capacity of a Class of Modulo-Sum Relay Channels. ISIT 2007: 596-600 - [i1]Marko Aleksic, Peyman Razaghi, Wei Yu:
Capacity of a Class of Modulo-Sum Relay Channels. CoRR abs/0704.3591 (2007) - 2006
- [j2]Rastislav Lukac, Konstantinos N. Plataniotis, Dimitrios Hatzinakos, Marko Aleksic:
A new CFA interpolation framework. Signal Process. 86(7): 1559-1579 (2006) - 2005
- [c6]Wei Yu, Marko Aleksic:
Coding for the blackwell channel: a survey propagation approach. ISIT 2005: 1583-1587 - [c5]Marko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija:
A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. PATMOS 2005: 724-732 - 2004
- [j1]Rastislav Lukac, Konstantinos N. Plataniotis, Dimitrios Hatzinakos, Marko Aleksic:
A novel cost effective demosaicing approach. IEEE Trans. Consumer Electron. 50(1): 256-261 (2004) - 2002
- [c4]Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija:
Comparative analysis of double-edge versus single-edge triggered clocked storage elements. ISCAS (5) 2002: 105-108 - [c3]Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija:
Conditional pre-charge techniques for power-efficient dual-edge clocking. ISLPED 2002: 56-59 - 2001
- [c2]Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija:
Timing Characterization of Dual-edge Triggered Flip-flops. ICCD 2001: 538-541 - [c1]Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija:
Conditional techniques for low power consumption flip-flops. ICECS 2001: 803-806
Coauthor Index
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