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Ting Wu 0003
Person information
- affiliation: Norel Systems, Tianjin, China
- affiliation: Rambus Inc., Los Altos, CA, USA
- affiliation (PhD 2007): Oregon State University, School of Electrical Engineering and Computer Science, Corvallis, OR, USA
Other persons with the same name
- Ting Wu — disambiguation page
- Ting Wu 0001
— Hangzhou Dianzi University, School of Cyberspace, Hangzhou, China (and 1 more)
- Ting Wu 0002 — RWTH Aachen University, Helmholtz Institute for Biomedical Engineering, Aachen, Germany
- Ting Wu 0004
- Ting Wu 0005
- Ting Wu 0006
- Ting Wu 0007
- Ting Wu 0008
- Ting Wu 0009
- Ting Wu 0010
- Ting Wu 0011
- Ting Wu 0012
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2010 – 2019
- 2012
- [j5]Amir Amirkhany, Jason Wei, Navin K. Mishra, Jie Shen, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris J. Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan:
A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface. IEEE J. Solid State Circuits 47(4): 911-925 (2012) - [j4]Kambiz Kaviani, Ting Wu, Jason Wei, Amir Amirkhany, Jie Shen, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris J. Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan:
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. IEEE J. Solid State Circuits 47(4): 926-937 (2012) - 2010
- [c7]Ting Wu, Farshid Aryanfar, Haechang Lee, Jie Shen, T. J. Chin, Carl W. Werner
Low-skew clock distribution using zero-phase-clock-buffer DLLs. ISSCC 2010: 176-177 - [c6]Leneesh Raghavan, Ting Wu:
Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link. VLSI Design 2010: 270-275
2000 – 2009
- 2009
- [j3]Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers. IEEE J. Solid State Circuits 44(2): 427-435 (2009) - [j2]Haechang Lee, Kun-Yung Ken Chang, Jung-Hoon Chun, Ting Wu, Yohan Frans, Brian S. Leibowitz, Nhat Nguyen, T. J. Chin, Kambiz Kaviani, Jie Shen, Xudong Shi, Wendemagegnehu T. Beyene, Simon Li, Reza Navid, Marko Aleksic, Fred S. Lee, Fredy Quan, Jared Zerbe, Rich Perego, Fariborz Assaderaghi:
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface. IEEE J. Solid State Circuits 44(4): 1235-1247 (2009) - 2008
- [c5]Ting Wu, Xudong Shi, Kambiz Kaviani, Haechang Lee, Jung-Hoon Chun, T. J. Chin, Jie Shen, Rich Perego, Ken Chang:
Clocking circuits for a 16Gb/s memory interface. CICC 2008: 435-438 - [c4]Igor Vytyaz, Josh Carnes, Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
Noise tolerant oscillator design using perturbation projection vector analysis. CICC 2008: 695-698 - 2007
- [j1]Ting Wu, Kartikeya Mayaram, Un-Ku Moon:
An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators. IEEE J. Solid State Circuits 42(4): 775-783 (2007) - [c3]Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop. CICC 2007: 547-550 - 2006
- [c2]Ting Wu, Un-Ku Moon, Kartikeya Mayaram:
Dependence of LC VCO oscillation frequency on bias current. ISCAS 2006 - 2005
- [c1]Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram:
An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications. ISCAS (4) 2005: 3986-3989
Coauthor Index
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