This paper describes a mobile memory interface with a narrow high-speed signal bus using low-swing voltage-mode signaling to achieve good active power ...

Mar 22, 2010 · This paper presents a 4.3 GB/s mobile memory interface that utilizes low power states with rapid transition times to support power efficient signaling.

This paper presents a 4.3 GB/s mobile memory interface that utilizes low power states with rapid transition times to support power efficient signaling over ...

Nguyen, "A 4.3GB/s mobile memory interface with power-efficient bandwidth scaling," IEEE Journal of Solid-State Circuits, vol 45, no. 4, pp. 889–898, 2010.

A 4.3 GB/s mobile memory interface with power-efficient bandwidth scaling. B ... A 32-Gb/s on-chip bus with driver pre-emphasis signaling. L Zhang, JM ...

A 4.3GB/s mobile memory interface built in TSMC 40nm LP CMOS uses burst transactions and low power states to enable power-efficient bandwidth scaling. A ...

Wilson, J., Aleksic, M, Greer, T., Bucher, M., Nguyen, N., "A 4.3GB/s Mobile Memory Interface with Power-efficient Bandwidth Scaling," Proceedings of 2009 ...

A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling · Computer Science, Engineering. IEEE Journal of Solid-State Circuits · 2010.

A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling · Computer Science, Engineering. IEEE Journal of Solid-State Circuits · 2010.

Feb 23, 2015 · Leibowitz et al, “A 4.3 GB/s mobile memory interface with power-efficient bandwidth scaling,” IEEE J. Solid-State Circuits, vol. 45, no. 4 ...