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Vikram Jain
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2020 – today
- 2024
- [c9]Man Shi, Vikram Jain, Antony Joseph, Maurice Meijer, Marian Verhelst:
BitWave: Exploiting Column-Based Bit-Level Sparsity for Deep Learning Acceleration. HPCA 2024: 732-746 - [c8]Joren Dumoulin, Pouya Houshmand, Vikram Jain, Marian Verhelst:
Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge. ISCAS 2024: 1-5 - [c7]Vikram Jain, Wei Tang, Zuoguo Wu, Viansa Schmulbach, Yakun Sophia Shao, Zhengya Zhang, Borivoje Nikolic:
Design Approach for Die-to-Die Interfaces to Enable Energy-Efficient Chiplet Systems. ISLPED 2024: 1-6 - 2023
- [j6]Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Kodai Ueyoshi, Ioannis A. Papistas, Man Shi, Qilin Zheng, Debjyoti Bhattacharjee, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst:
DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge. IEEE J. Solid State Circuits 58(1): 203-215 (2023) - [j5]Vikram Jain, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Linyan Mei, Bert Boons, Marian Verhelst:
TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge. IEEE J. Solid State Circuits 58(8): 2360-2371 (2023) - [c6]Vikram Jain, Matheus A. Cavalcante, Nazareno Bruschi, Michael Rogenmoser, Thomas Benz, Andreas Kurth, Davide Rossi, Luca Benini, Marian Verhelst:
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge. DAC 2023: 1-6 - [c5]Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, Sam Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal:
PetaOps/W edge-AI $\mu$ Processors: Myth or reality? DATE 2023: 1-6 - [i4]Vikram Jain, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Linyan Mei, Bert Boons, Marian Verhelst:
TinyVers: A Tiny Versatile System-on-chip with State-Retentive eMRAM for ML Inference at the Extreme Edge. CoRR abs/2301.03537 (2023) - [i3]Vikram Jain, Matheus A. Cavalcante, Nazareno Bruschi, Michael Rogenmoser, Thomas Benz, Andreas Kurth, Davide Rossi, Luca Benini, Marian Verhelst:
PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge. CoRR abs/2308.00154 (2023) - 2022
- [j4]Vikram Jain, Ninad Jadhav, Marian Verhelst:
Enabling real-time object detection on low cost FPGAs. J. Real Time Image Process. 19(1): 217-229 (2022) - [c4]Kodai Ueyoshi, Ioannis A. Papistas, Pouya Houshmand, Giuseppe Maria Sarda, Vikram Jain, Man Shi, Qilin Zheng, Juan Sebastian Piedrahita Giraldo, Peter Vrancx, Jonas Doevenspeck, Debjyoti Bhattacharjee, Stefan Cosemans, Arindam Mallik, Peter Debacker, Diederik Verkest, Marian Verhelst:
DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. ISSCC 2022: 1-3 - [c3]Vikram Jain, Juan Sebastian Piedrahita Giraldo, Jaro De Roose, Bert Boons, Linyan Mei, Marian Verhelst:
TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge. VLSI Technology and Circuits 2022: 20-21 - [i2]Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Frank K. Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, S. Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal:
CONVOLVE: Smart and seamless design of smart edge processors. CoRR abs/2212.00873 (2022) - 2021
- [j3]Linyan Mei, Pouya Houshmand, Vikram Jain, Juan Sebastian Piedrahita Giraldo, Marian Verhelst:
ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators. IEEE Trans. Computers 70(8): 1160-1174 (2021) - [j2]Vikram Jain, Christoffer Fougstedt, Per Larsson-Edefors:
Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 25-34 (2021) - [j1]Juan Sebastian Piedrahita Giraldo, Vikram Jain, Marian Verhelst:
Efficient Execution of Temporal Convolutional Networks for Embedded Keyword Spotting. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2220-2228 (2021) - [c2]Vikram Jain, Linyan Mei, Marian Verhelst:
Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks. AICAS 2021: 1-4 - 2020
- [i1]Linyan Mei, Pouya Houshmand, Vikram Jain, Juan Sebastian Piedrahita Giraldo, Marian Verhelst:
ZigZag: A Memory-Centric Rapid DNN Accelerator Design Space Exploration Framework. CoRR abs/2007.11360 (2020)
2010 – 2019
- 2019
- [c1]Vikram Jain, Christoffer Fougstedt, Per Larsson-Edefors:
Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication. ICECS 2019: 45-48
Coauthor Index
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