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10th DTIS 2015: Napoli, Italy
- 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2015, Napoli, Italy, April 21-23, 2015. IEEE 2015, ISBN 978-1-4799-1999-4
- Paolo Prinetto, Giorgio Di Natale:
DTIS 2015 foreword. 1 - Said Hamdioui:
Electronics and computing in nano-era: The good, the bad and the challenging. 1 - Khaled Salah:
A TSV to TSV, A TSV to Metal interconnects, and A TSV to active device coupling capacitance: Analysis and recommendations. 1-2 - Minas Dasygenis
, Ioannis Petrousov:
A generic moduli selection algorithm for the Residue Number System. 1-2 - Sawssen Lahiani, Dorra Ayadi, Samir Ben Salem, Skandar Douss, Mourad Loulou:
Variable Gain Amplifier in CMOS 0.18µm for WiMAX application. 1-2 - Rasoul Jafari, Elham Zahraei Salehi, Zain Navabi:
Utilizing NOPs for online deterministic testing of simple processing cores. 1-2 - Abdelghani Dendouga, Slimane Oussalah
Comparative study of two CMOS operational amplifiers for high performance pipelined ADC. 1-2 - Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
Scan-chain intra-cell defects grading. 1-6 - Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi
An effective ATPG flow for Gate Delay Faults. 1-6 - Amirreza Nekooei, Zainalabedin Navabi:
Multi-valued logic test access mechanism for test time and power reduction. 1-6 - Andreas Christos Demartinos, Andreas Tsimpos, Spiros Vlassis, Savvas Sgourenas, George Souliotis
A 3GHz VCO suitable for MIPI M-PHY serial interface. 1-6 - Andreas Tsimpos, George Souliotis
All digital phase interpolator. 1-6 - Sherif M. Saif, Mohamed Dessouky, Hazem M. Abbas
Analog layout constraints resolution and shape function generation using Satisfiability Modulo Theories. 1-6 - Francesco Regazzoni:
Physical attacks, introduction and application to embedded processors. 1 - Álvaro Gómez-Pau, Luz Balado, Joan Figueras:
Analog circuits testing using digitally coded indirect measurements. 1-6 - Jose Domingos Alves, Guiomar Evans
A digital pseudorandom uniform noise generator for ADC built-in self-test. 1-6 - Yong Zhao, Hans G. Kerkhoff:
Application of functional IDDQ testing in a VLIW processor towards detection of aging degradation. 1-5 - Mario Barbareschi
Testing 90 nm microcontroller SRAM PUF quality. 1-6 - Mario Barbareschi
Supply voltage variation impact on Anderson PUF quality. 1-6 - Marie-Lise Flottes, Sophie Dupuis, Papa-Sidi Ba, Bruno Rouzeyre:
On the limitations of logic testing for detecting Hardware Trojans Horses. 1-5 - Zainalabedin Navabi:
HDLs evolve as they affect design methodology for a higher abstraction and a better integration. 1 - Khaled Khalifa, Khaled Salah:
Implementation and verification of a generic universal memory controller based on UVM. 1-2 - Minas Dasygenis
A networking EDA tool for multi-vector multiplication IP circuits. 1-2 - Ioannis Voyiatzis, Cleo Sgouropoulou
A concurrent BIST scheme for read only memories. 1-2 - Alessandro Grossi, Cristian Zambelli
Automated characterization of TAS-MRAM test arrays. 1-2 - Somayeh Sadeghi Kohan, Mehdi Kamal, John McNeil
Online self adjusting progressive age monitoring of timing variations. 1-2 - Ioannis Voyiatzis, Cleo Sgouropoulou
Detecting untestable hardware Trojan with non-intrusive concurrent on line testing. 1-2 - Maha Kooli, Alberto Bosio, Pascal Benoit, Lionel Torres:
Software testing and software fault injection. 1-6 - Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Stefan Cosemans, Pieter Weckx, Praveen Raghavan, Francky Catthoor:
Comparative analysis of RD and Atomistic trap-based BTI models on SRAM Sense Amplifier. 1-6 - Camillo Stefanucci, Pietro Buccella, Maher Kayal, Jean-Michel Sallese:
Modeling avalanche breakdown for ESD diodes in integrated circuits. 1-3 - Somayeh Sadeghi Kohan, Arezoo Kamran
Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation. 1-6 - Mehdi Sedighi, Foroogh Haddadi, Samaneh Emami
A heuristic algorithm for high level synthesis of decimal arithmetic circuits using SystemC. 1-6 - Frank Wawrzik, William Chipman, Javier Moreno Molina, Christoph Grimm
Modeling and simulation of Cyber-Physical Systems with SICYPHOS. 1-6 - Carna Radojicic, Thiyagarajan Purusothaman, Christoph Grimm
Towards formal validation: Symbolic simulation of SystemC models. 1-6 - Peyman Pouyan, Esteve Amat
Statistical lifetime analysis of memristive crossbar matrix. 1-6 - Yuanfan Yang, Jimson Mathew, Marco Ottavi
2T2M memristor based TCAM cell for low power applications. 1-6 - Chris Van Hoof:
Frictionless wearable technology: The key to unleashing the power of wearable sensors for health and lyfestyle. 1 - Mehran Goli
Application-specific power-aware mapping for reconfigurable NoC architectures. 1-6 - Muhammad Adeel Pasha, Bilal Siddiqui, Umer Farooq:
A design-flow for high-level synthesis and resource estimation of reconfigurable architectures. 1-6 - Saif-Ur Rehman, Mounir Benabdenbi, Lorena Anghel:
Application-independent testing of multilevel interconnect in mesh-based FPGAs. 1-6 - Alessandro Palla
Wearable speech enhancement system based on MEMS microphone array for disabled people. 1-5 - Massimiliano Donati
A modular suite to support human-smartphone interaction for people with motor skill impairments. 1-5 - Valerio F. Annese
Gait analysis for fall prediction using EMG triggered movement related potentials. 1-6 - Dennis Noll, Udo Schwalke:
Silicon CMOS compatible in situ CCVD growth of graphene on silicon nitride. 1-3 - Ahmed Abo-Elhadeed, Pascal Bolcato:
A simple numerical modeling technique for PSP-NQS differential equation. 1-4 - Pranab Roy, Pampa Howladar, Raja Dastidar, Hafizur Rahaman
3D integration in biochips: New proposed architectures for 3D applications in ATDA based digital microfluidic biochips. 1-6 - Giuseppe Airo Farulla, Ludovico Orlando Russo, Stefano Rosa
ORIENTOMA: A novel platform for autonomous and safe navigation for blind and visually impaired. 1-6 - Miguel Efrain Kaouk Ng, Stefano Primatesta
A cloud robotics system for telepresence enabling mobility impaired people to enjoy the whole museum experience. 1-6 - Frederik Gossen:
Bayesian recognition of human identities from continuous visual features for safe and secure access in healthcare environments. 1-5 - Tiziana Margaria:
Why caring about leading-edge software engineering in healthcare and assistive technology applications? 1 - Ioannis Voyiatzis, Dimitris J. Kavvadias, S. Sinitos, K. Vlahantonis, P. Kyrkos, Cleo Sgouropoulou
Test set embedding into hardware generated sequences using an embedding algorithm. 1-2 - Roberta Piscitelli, Shivam Bhasin, Francesco Regazzoni
Fault attacks, injection techniques and tools for simulation. 1-6 - Elena I. Vatajelu
STT-MRAM cell reliability evaluation under process, voltage and temperature (PVT) variations. 1-6
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