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Nico Jossart
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2020 – today
- 2024
- [c7]W. Kim, Valerio Pica
, N. Jossart, Farrukh Yasin, Kurt Wostyn, S. Couet, Sidharth Rao:
A novel test and analysis scheme to elucidate tail bit characteristics in STT-MRAM arrays. IMW 2024: 1-4 - 2023
- [c6]Simon Van Beek, Kaiming Cai, Kaiquan Fan, Giacomo Talmelli, Anna Trovato, Nico Jossart, Siddharth Rao, Adrian Vaisman Chasin, Sebastien Couet:
MTJ degradation in multi-pillar SOT-MRAM with selective writing. IRPS 2023: 1-7 - 2022
- [c5]Simon Van Beek, Kaiming Cai
MTJ degradation in SOT-MRAM by self-heating-induced diffusion. IRPS 2022: 4 - 2021
- [c4]Sidharth Rao
STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application. IMW 2021: 1-4 - [c3]Simon Van Beek, Siddharth Rao
Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution. IRPS 2021: 1-5
2010 – 2019
- 2019
- [c2]Kevin Garello, Farrukh Yasin, Hubert Hody, S. Couet
Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM. VLSI Circuits 2019: 194- - 2018
- [c1]Kevin Garello, Kevin Garello Yasin, S. Couet, Laurent Souriau
SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories. VLSI Circuits 2018: 81-82 - [i1]Kevin Garello, Farrukh Yasin, S. Couet, Laurent Souriau, Johan Swerts, Sidharth Rao, Simon Van Beek, Wonsub Kim, Enlong Liu, Shreya Kundu, Diana Tsvetanova, N. Jossart, Kris Croes, E. Grimaldi, M. Baumgartner, D. Crotti, Arnaud Furnémont, Pietro Gambardella, Gouri Sankar Kar:
SOT-MRAM 300mm integration for low power and ultrafast embedded memories. CoRR abs/1810.10356 (2018)
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last updated on 2024-11-13 23:49 CET by the dblp team
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