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Kai-Hui Chang
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2010 – 2019
- 2019
- [c27]Li-Jie Chen, Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
, Chi-Lai Huang:
Path controllability analysis for high quality designs. ASP-DAC 2019: 687-692 - 2016
- [j10]Kai-Hui Chang, Hong-Zu Chou, Haiqian Yu, Dylan Dobbyn, Sy-Yen Kuo
Handling Nondeterminism in Logic Simulation so That Your Waveform Can Be Trusted Again. IEEE Des. Test 33(6): 63-71 (2016) - 2015
- [c26]Ting-Wei Chiang, Kai-Hui Chang, Yen-Ting Liu, Jie-Hong R. Jiang:
Scalable sequence-constrained retention register minimization in power gating design. DAC 2015: 130:1-130:6 - 2014
- [c25]Kai-Hui Chang, Yen-Ting Liu, Chris Browy:
Automated methods for eliminating X bugs. ISQED 2014: 597-603 - 2012
- [j9]Kai-Hui Chang, Chris Browy:
Parallel Logic Simulation: Myth or Reality? Computer 45(4): 67-73 (2012) - [c24]Kai-Hui Chang, Chris Browy:
Improving gate-level simulation accuracy when unknowns exist. DAC 2012: 936-940 - [c23]Kai-Hui Chang, Hong-Zu Chou, Igor L. Markov:
RTL analysis and modifications for improving at-speed test. DATE 2012: 400-405 - [c22]Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu:
Improving design verifiability by early RTL coverability analysis. MEMOCODE 2012: 25-32 - [c21]Kai-Hui Chang, Chia-Wei Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu:
Reducing test point overhead with don't-cares. MWSCAS 2012: 534-537 - 2011
- [c20]Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
Facilitating unreachable code diagnosis and debugging. ASP-DAC 2011: 485-490 - [c19]Chih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, Sy-Yen Kuo:
Formal reset recovery slack calculation at the register transfer level. DATE 2011: 571-574 - [c18]Chih-Neng Chung, Chia-Wei Chang, Kai-Hui Chang, Sy-Yen Kuo
Applying verification intention for design customization via property mining under constrained testbenches. ICCD 2011: 84-89 - [c17]Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu, Chiu-Han Hsiao, Sy-Yen Kuo
Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization. ISQED 2011: 174-181 - 2010
- [j8]Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
Accurately Handle Don't-Care Conditions in High-Level Designs and Application for Reducing Initialized Registers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(4): 646-651 (2010) - [j7]Kai-Hui Chang, Valeria Bertacco, Igor L. Markov, Alan Mishchenko:
Logic synthesis and circuit customization using extensive external don't-cares. ACM Trans. Design Autom. Electr. Syst. 15(3): 26:1-26:24 (2010) - [c16]Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo
Optimizing blocks in an SoC using symbolic code-statement reachability analysis. ASP-DAC 2010: 787-792 - [c15]Hong-Zu Chou, Haiqian Yu, Kai-Hui Chang, Dylan Dobbyn, Sy-Yen Kuo:
Finding reset nondeterminism in RTL designs - scalable X-analysis methodology and case study. DATE 2010: 1494-1499
2000 – 2009
- 2009
- [b2]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Functional Design Errors in Digital Circuits - Diagnosis, Correction and Repair. Lecture Notes in Electrical Engineering 32, Springer 2009, ISBN 978-1-4020-9364-7, pp. 3-185 [contents] - [j6]Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco:
Incremental Verification with Error Detection, Diagnosis, and Visualization. IEEE Des. Test Comput. 26(2): 34-43 (2009) - [c14]Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo:
Handling don't-care conditions in high-level synthesis and application for reducing initialized registers. DAC 2009: 412-415 - [c13]Kai-Hui Chang, Valeria Bertacco, Igor L. Markov:
Customizing IP cores for system-on-chip designs using extensive external don't-cares. DATE 2009: 582-585 - [c12]Hong-Zu Chou, I-Hui Lin, Ching-Sung Yang, Kai-Hui Chang, Sy-Yen Kuo
Enhancing bug hunting using high-level symbolic simulation. ACM Great Lakes Symposium on VLSI 2009: 417-420 - 2008
- [j5]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Automating Postsilicon Debugging and Repair. Computer 41(7): 47-54 (2008) - [j4]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
SafeResynth: A new technique for physical synthesis. Integr. 41(4): 544-556 (2008) - [j3]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Fixing Design Errors With Counterexamples and Resynthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 184-188 (2008) - [c11]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Reap what you sow: spare cells for post-silicon metal fix. ISPD 2008: 103-110 - 2007
- [b1]Kai-Hui Chang:
Functional design error diagnosis, correction and layout repair of digital circuits. University of Michigan, USA, 2007 - [j2]Kai-Hui Chang, Valeria Bertacco, Igor L. Markov:
Simulation-Based Bug Trace Minimization With BMC-Based Refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1): 152-165 (2007) - [j1]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Postplacement rewiring by exhaustive search for functional symmetries. ACM Trans. Design Autom. Electr. Syst. 12(3): 32:1-32:21 (2007) - [c10]Stephen Plaza, Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Node Mergers in the Presence of Don't Cares. ASP-DAC 2007: 414-419 - [c9]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Safe Delay Optimization for Physical Synthesis. ASP-DAC 2007: 628-633 - [c8]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Fixing Design Errors with Counterexamples and Resynthesis. ASP-DAC 2007: 944-949 - [c7]Kai-Hui Chang, Ilya Wagner, Valeria Bertacco, Igor L. Markov:
Automatic error diagnosis and correction for RTL designs. HLDVT 2007: 65-72 - [c6]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Automating post-silicon debugging and repair. ICCAD 2007: 91-98 - [c5]Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco:
InVerS: An Incremental Verification System with Circuit Similarity Metrics and Error Visualization. ISQED 2007: 487-494 - 2005
- [c4]Kai-Hui Chang, Jeh-Yen Kang, Han-Wei Wang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo:
Automatic Partitioner for Behavior Level Distributed Logic Simulation. FORTE 2005: 525-528 - [c3]Kai-Hui Chang, Igor L. Markov, Valeria Bertacco:
Post-placement rewiring and rebuffering by exhaustive search for functional symmetries. ICCAD 2005: 56-63 - [c2]Kai-Hui Chang, Valeria Bertacco, Igor L. Markov:
Simulation-based bug trace minimization with BMC-based refinement. ICCAD 2005: 1045-1051 - 2004
- [c1]Kai-Hui Chang, Wei-Ting Tu, Yi-Jong Yeh, Sy-Yen Kuo:
A Temporal Assertion Extension to Verilog. ATVA 2004: 499-504
Coauthor Index
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