research-article

Scalable sequence-constrained retention register minimization in power gating design

Authors:

Ting-Wei Chiang,

Jie-Hong R. JiangAuthors Info & Claims

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

Article No.: 130, Pages 1 - 6

https://doi.org/10.1145/2744769.2744905

Published: 07 June 2015 Publication History

Abstract

Retention registers are utilized in power gating design to hold design state during power down and to allow safe and fast system reactivation. Since a retention register consumes more power and costs more area than a non-retention register, it is desirable to minimize the use of retention registers. However, relaxing retention requirement to a minimal subset of registers can be computationally challenging. In this paper, we adopt satisfiability solving for scalable selection of registers whose retention is unnecessary and exploit input sequence constraints to increase the number of non-retention registers. Empirical results on industrial benchmarks show that our proposed methods are efficient and effective in identifying non-retention registers.

References

[1]

Avery Design Systems Inc., http://www.avery-design.com.

[2]

K.-H. Chang, Y.-T. Liu, C. S. Browy, and C.-L. Huang. Systems and methods for partial retention synthesis, US Patent 8938705, 2014.

[3]

Y.-G. Chen, Y. Shi, K.-Y. Lai, G. Hui, and S.-C. Chang. Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms. In Proceedings of the International Conference on Computer-Aided Design (ICCAD), pages 309--316, 2012.

Digital Library

[4]

H.-Z. Chou, K.-H. Chang, and S.-Y. Kuo. Handling don't-care conditions in high-level synthesis and application for reducing initialized registers. In Proceedings of the Design Automation Conference (DAC), pages 412--415, 2009.

Digital Library

[5]

H.-Z. Chou, K.-H. Chang, and S.-Y. Kuo. Accurately handle don't-care conditions in high-level designs and application for reducing initialized registers. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(4):646--651, April 2010.

Digital Library

[6]

H.-Z. Chou, H. Yu, K.-H. Chang, D. Dobbyn, and S.-Y. Kuo. Finding reset nondeterminism in RTL designs - scalable X-analysis methodology and case study. In Proceedings of the Design, Automation and Test in Europe Conference (DATE), pages 1494--1499, 2010.

Digital Library

[7]

A. Darbari, B. Al-Hashimi, D. Flynn, and J. Biggs. Selective state retention design using symbolic simulation. In Proceedings of the Design, Automation and Test in Europe Conference (DATE), pages 1644--1649, 2009.

Digital Library

[8]

N. Eén and N. Sörensson. An extensible SAT-solver. In Proceedings of the International Conference on Theory and Applications of Satisfiability Testing (SAT), pages 502--518, 2003.

[9]

S. Greenberg, J. Rabinowicz, and E. Manor. Selective state retention power gating based on formal verification. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(3):807--815, December 2014.

[10]

S. Greenberg, J. Rabinowicz, R. Tsechanski, and E. Paperno. Selective state retention power gating based on gate-level analysis. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(4):1095--1104, April 2014.

[11]

J.-H. Jiang, C.-C. Lee, A. Mishchenko, and C.-Y. Huang. To SAT or not to SAT: Scalable exploration of functional dependency. IEEE Transactions on Computers, 59(4):457--467, April 2010.

Digital Library

[12]

K. McMillan. Applying SAT methods in unbounded symbolic model checking. In Proceedings of the International Conference on Computer Aided Verification (CAV), pages 250--264, 2002.

Digital Library

[13]

M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient SAT solver. In Proceedings of the Design Automation Conference (DAC), pages 530--535, 2001.

Digital Library

[14]

A. Smith, A. Veneris, and A. Viglas. Design diagnosis using Boolean satisfiability. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), pages 218--223, 2004.

Digital Library

[15]

Y. Tian, A. Nilipour, and A. Thiriveedhi. Partial state retention verification - challenges and techniques. In Proceedings of the Design Automation Conference (DAC), Designer Track Poster 15D.6, 2013.

[16]

G. Tseitin. On the complexity of derivation in propositional calculus. In Studies in Constructive Mathematics and Mathematical Logic, pages 466--483, 1970.

[17]

Y. Yu, P. Subramanyan, N. Tsiskaridze, and S. Malik. All-SAT using minimal blocking clauses. In Proceedings of the International Conference on VLSI Design, pages 86--91, 2014.

Digital Library

Cited By

Rabinowicz JGreenberg S(2021)A New Physical Design Flow for a Selective State Retention Based ApproachJournal of Low Power Electronics and Applications10.3390/jlpea1103003511:3(35)Online publication date: 13-Sep-2021
https://doi.org/10.3390/jlpea11030035
Kim TPark HKim T(2021)Allocation of Always-On State Retention Storage for Power Gated Circuits—Steady-State- Driven ApproachIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.304705629:3(499-511)Online publication date: Mar-2021
https://doi.org/10.1109/TVLSI.2020.3047056
Fan GLin MParameswaran S(2017)State retention for power gated design with non-uniform multi-bit retention latchesProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199781(607-614)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199781
Show More Cited By

Index Terms

Scalable sequence-constrained retention register minimization in power gating design
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis

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cover image ACM Conferences

DAC '15: Proceedings of the 52nd Annual Design Automation Conference

June 2015

1204 pages

ISBN:9781450335201

DOI:10.1145/2744769

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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New York, NY, United States

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Published: 07 June 2015

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DAC '15: The 52nd Annual Design Automation Conference 2015

June 7 - 11, 2015

California, San Francisco

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Cited By

Rabinowicz JGreenberg S(2021)A New Physical Design Flow for a Selective State Retention Based ApproachJournal of Low Power Electronics and Applications10.3390/jlpea1103003511:3(35)Online publication date: 13-Sep-2021
https://doi.org/10.3390/jlpea11030035
Kim TPark HKim T(2021)Allocation of Always-On State Retention Storage for Power Gated Circuits—Steady-State- Driven ApproachIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2020.304705629:3(499-511)Online publication date: Mar-2021
https://doi.org/10.1109/TVLSI.2020.3047056
Fan GLin MParameswaran S(2017)State retention for power gated design with non-uniform multi-bit retention latchesProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199781(607-614)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199781
Fan GLin M(2017)State retention for power gated design with non-uniform multi-bit retention latches2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2017.8203833(607-614)Online publication date: Nov-2017
https://doi.org/10.1109/ICCAD.2017.8203833
Wang NWang HJin YYe J(2017)Integrating operation scheduling and binding for functional unit power-gating in high-level synthesis2017 IEEE 12th International Conference on ASIC (ASICON)10.1109/ASICON.2017.8252679(1129-1132)Online publication date: Oct-2017
https://doi.org/10.1109/ASICON.2017.8252679
Wang NChen SMa ZLing XZhu Y(2017)Integrating operation scheduling and binding for functional unit power-gating in high-level synthesisIntegration, the VLSI Journal10.1016/j.vlsi.2017.11.008Online publication date: Dec-2017
https://doi.org/10.1016/j.vlsi.2017.11.008

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