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Gil-Cho Ahn
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2020 – today
- 2024
- [c25]Kang-Il Cho, Jun-Ho Boo, Jae-Geun Lim, Gil-Cho Ahn:
A CMOS Analog Front-End for Hall Sensor Readout IC. ICEIC 2024: 1-3 - 2023
- [j19]Ho-Jin Kim
, Jun-Ho Boo
A Single-Loop Third-Order 10-MHz BW Source-Follower-Integrator Based Discrete-Time Delta-Sigma ADC. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 401-405 (2023) - [c24]Seong-Bo Park, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Won-Jun Cho, Gil-Cho Ahn:
A Second-Order DT Delta-Sigma Modulator with Noise-Shaping SAR Quantizer. ISOCC 2023: 89-90 - [c23]Mi-Ji Go, Jun-Ho Boo, Jae-Geun Lim, Hyoung-Jung Kim, Jae-Hyuk Lee, Seong-Bo Park, Byeongho Yu, Won-Jun Cho, Gil-Cho Ahn:
A 12-bit 3-MS/s Synchronous SAR ADC With a Hybrid RC DAC. ISOCC 2023: 191-192 - 2022
- [c22]Hyoung-Jung Kim, Jae-Hyuk Lee, Jae-Geun Lim, Jun-Ho Boo, Ho-Jin Kim, Seong-Bo Park, Youngdon Choi, Jung-Hwan Choi, Gil-Cho Ahn:
A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling Capacitor. ISOCC 2022: 235-236 - 2021
- [j18]Jun-Ho Boo
A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, -0.12% for Battery-Monitoring Applications. IEEE J. Solid State Circuits 56(4): 1197-1206 (2021) - [j17]Ju-Hye Han
A 96dB Dynamic Range 2kHz Bandwidth 2nd Order Delta-Sigma Modulator Using Modified Feed-Forward Architecture With Delayed Feedback. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1645-1649 (2021) - [c21]Yong-Sik Kwak, Ho-Jin Kim, Kang-Il Cho, Jun-Ho Boo, Gil-Cho Ahn:
A 0.9V 0.022mm2 103dB DR Switched-Capacitor Audio Delta-Sigma Modulator Using Input-Referred kT/C Noise Reduction Technique. A-SSCC 2021: 1-3 - 2020
- [c20]Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, Jun-Sang Park, Seung-Hoon Lee, Gil-Cho Ahn:
A 10-b 900-MS/s Single-Channel Pipelined-SAR ADC Using Current-Mode Reference Scaling. A-SSCC 2020: 1-2 - [c19]Jun-Sang Park, Je-Min Jeon, Jun-Ho Boo, Jae-Hyuk Lee, Kang-Il Cho, Ho-Jin Kim, Gil-Cho Ahn, Seung-Hoon Lee:
A 2.2mW 12-bit 200MS/s 28nm CMOS Pipelined SAR ADC with Dynamic Register-Based High-Speed SAR Logic. A-SSCC 2020: 1-2 - [c18]Tae-Gwan Kim, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, Gil-Cho Ahn:
A Third-Order DT Delta-Sigma Modulator With Noise-Coupling Technique. ISOCC 2020: 3-4 - [c17]Jun-Ho Boo, Kang-Il Cho, Ho-Jin Kim, Jae-Geun Lim, Yong-Sik Kwak, Seung-Hoon Lee, Gil-Cho Ahn:
A Single-Trim Switched Capacitor CMOS Bandgap Reference with a 3σ Inaccuracy of +0.02%, -0.12% for Battery Monitoring Applications. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j16]Jun-Sang Park
A 12.1 fJ/Conv.-Step 12b 140 MS/s 28-nm CMOS Pipelined SAR ADC Based on Energy-Efficient Switching and Shared Ring Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 66-II(7): 1119-1123 (2019) - [c16]Kang-Il Cho, Yong-Sik Kwak, Ho-Jin Kim, Jun-Ho Boo, Seung-Hoon Lee, Gil-Cho Ahn:
A 10-b 320-MS/s Dual-Residue Pipelined SAR ADC with Binary Search Current Interpolator. CICC 2019: 1-4 - [c15]Jun-Young Kil, Kang-Il Cho, Ho-Jin Kim, Jun-Ho Boo, Yong-Sik Kwak, Gil-Cho Ahn:
A 101 dB Dynamic Range Delta-Sigma Modulator Using Modified Feed-Forward Architecture for Audio Application. ISOCC 2019: 7-8 - 2018
- [j15]Kang-Il Cho, Yong-Sik Kwak, Ho-Jin Kim, Gil-Cho Ahn:
A 101 dB dynamic range, 2 kHz bandwidth delta-sigma modulator with a modified feed-forward architecture. IEICE Electron. Express 15(21): 20180848 (2018) - [j14]Himchan Park, Qiwei Huang, Changzhi Yu, Seulki Kim, Gil-Cho Ahn, Jinwook Burm:
Two CMOS time to digital converters using successive approximation register logic. IEICE Electron. Express 15(22): 20180840 (2018) - [j13]Yong-Sik Kwak
A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Resolution-Enhanced Sturdy MASH Delta-Sigma Modulator Using Source-Follower-Based Integrators. IEEE J. Solid State Circuits 53(10): 2772-2782 (2018) - [j12]Tai-Ji An
Area-Efficient Time-Shared Digital-to-Analog Converter With Dual Sampling for AMOLED Column Driver IC's. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3227-3240 (2018) - 2017
- [j11]Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Gil-Cho Ahn:
A 1.8 V 89.2 dB dynamic range delta-sigma modulator using an op-amp dynamic current biasing technique. IEICE Electron. Express 14(21): 20171007 (2017) - [c14]Yong-Sik Kwak, Kang-Il Cho, Ho-Jin Kim, Seung-Hoon Lee, Gil-Cho Ahn:
A 72.9-dB SNDR 20-MHz BW 2-2 discrete-time sturdy MASH delta-sigma modulator using source-follower-based integrators. A-SSCC 2017: 289-292 - [c13]Bum-Sik Chung, Hyeong-Kyu Kim, Kang-Il Cho, Ho-Jin Kim, Gil-Cho Ahn:
Analog front-end for EMG acquisition system. ISOCC 2017: 57-58 - 2014
- [c12]Mi-rim Kim, Young-Ouk Kim, Yong-Sik Kwak, Gil-Cho Ahn:
A 12-bit 200-kS/s SAR ADC with hybrid RC DAC. APCCAS 2014: 185-188 - 2013
- [c11]Tai-Ji An, Jun-Sang Park, Yongmin Kim, Suk-Hee Cho, Gil-Cho Ahn, Seung-Hoon Lee:
10b 150MS/s 0.4mm2 45nm CMOS ADC based on process-insensitive amplifiers. ISCAS 2013: 316- - 2012
- [c10]Young-min Park, Tae-In Kwon, Kang-Il Cho, Yong-Sik Kwak, Gil-Cho Ahn, Chang-Seob Shin, Myung-Jin Lee, Seung-Bin You, Ho-Jin Park:
A 1.1 V 82.3dB audio ΔΣ ADC using asynchronous SAR type quantizer. ICECS 2012: 637-640 - [c9]Yong-Sik Kwak, Kwang-Soo Kim, Gil-Cho Ahn:
A 1.8 V 89.2 dB delta-sigma adc for sensor interface with on-chip reference. ISCAS 2012: 520-523 - [c8]Jae-Hyeon Shin, Kang-Il Cho, Gil-Cho Ahn:
A digitally enhanced low-distortion delta-sigma modulator for wideband application. ISOCC 2012: 108-111 - [c7]Sang-Pil Nam, Yongmin Kim, Dong-Hyun Hwang, Hyo-Jin Kim, Tai-Ji An, Jun-Sang Park, Suk-Hee Cho, Gil-Cho Ahn, Seung-Hoon Lee:
A 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC for analog TV applications. ISOCC 2012: 124-127 - 2011
- [j10]Byeong-Woo Koo, Seung-Jae Park, Gil-Cho Ahn, Seung-Hoon Lee:
A Single Amplifier-Based 12-bit 100 MS/s 1 V 19 mW 0.13 µm CMOS ADC with Various Power and Area Minimized Circuit Techniques. IEICE Trans. Electron. 94-C(8): 1282-1288 (2011) - [j9]Hee-Cheol Choi, Pil-Seon Yoo, Gil-Cho Ahn, Seung-Hoon Lee:
A 14b 150 MS/s 140 mW 2.0 mm2 0.13µm CMOS A/D converter for software-defined radio systems. Int. J. Circuit Theory Appl. 39(2): 135-147 (2011) - [j8]Chang-Seob Shin, Gil-Cho Ahn:
A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique. IEEE Trans. Circuits Syst. II Express Briefs 58-II(5): 274-278 (2011) - [c6]Chang-Seob Shin, Min-Ho Yoon, Kang-Il Cho, Young-Ju Kim, Kwang-Soo Kim, Seung-Hoon Lee, Gil-Cho Ahn:
A 6.25 MHz BW 8-OSR fifth-order single-stage sigma-delta ADC. ISCAS 2011: 1117-1120 - [c5]Jin-Seon Kim, Tae-In Kwon, Gil-Cho Ahn, Yi-Gyeong Kim, Jong-Kee Kwon:
A ΔΣ ADC using 4-bit SAR type quantizer for audio applications. ISOCC 2011: 73-75 - 2010
- [j7]Young-Ju Kim, Hee-Cheol Choi, Gil-Cho Ahn, Seung-Hoon Lee:
A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp. IEEE J. Solid State Circuits 45(3): 620-628 (2010) - [c4]Xicheng Jiang, Jungwoo Song, Todd Brooks, Jianlong Chen, Vinay Chandrasekhar, Felix Cheung, Sherif Galal, Darwin Cheung, Gil-Cho Ahn, Madhulatha Bonu:
A 10mW stereo audio CODEC in 0.13µm CMOS. ISSCC 2010: 82-83
2000 – 2009
- 2009
- [j6]Seung-Hoon Lee, Young-Ju Kim, Hee-Cheol Choi, Gil-Cho Ahn:
A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(5): 894-901 (2009) - [c3]Young-Ju Kim, Hee-Cheol Choi, Kyung-Hoon Lee, Gil-Cho Ahn, Seung-Hoon Lee, Ju-Hwa Kim, Kyoung-Jun Moon, Michael Choi, Kyoung-Ho Moon, Ho-Jin Park, Byeong-Ha Park:
A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers. CICC 2009: 271-274 - 2008
- [j5]Min-Gyu Kim, Gil-Cho Ahn, Pavan Kumar Hanumolu, Sanghyeon Lee, Sang-Ho Kim, Seung-Bin You, Jae-Whui Kim, Gabor C. Temes, Un-Ku Moon:
A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC. IEEE J. Solid State Circuits 43(5): 1195-1206 (2008) - 2007
- [c2]Gil-Cho Ahn, Min-Gyu Kim, Pavan Kumar Hanumolu, Un-Ku Moon:
A 1V 10b 30MSPS Switched-RC Pipelined ADC. CICC 2007: 325-328 - 2005
- [j4]Jipeng Li, Gil-Cho Ahn, Dong-Young Chang, Un-Ku Moon:
A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR. IEEE J. Solid State Circuits 40(4): 960-969 (2005) - [j3]Gil-Cho Ahn, Dong-Young Chang, Matthew E. Brown, Naoto Ozaki, Hiroshi Youra, Ken Yamamura, Koichi Hamashita, Kaoru Takasuka, Gábor C. Temes, Un-Ku Moon:
A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators. IEEE J. Solid State Circuits 40(12): 2398-2407 (2005) - [j2]Dong-Young Chang, Gil-Cho Ahn, Un-Ku Moon:
Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(1): 1-12 (2005) - 2004
- [c1]Min-Gyu Kim, Gil-Cho Ahn, Un-Ku Moon:
An improved algorithmic ADC clocking scheme. ISCAS (1) 2004: 589-592
1990 – 1999
- 1996
- [j1]Gil-Cho Ahn, Hee-Cheol Choi, Shin-Il Lim, Seung-Hoon Lee, Chul-Dong Lee:
A 12-b, 10-MHz, 250-mW CMOS A/D converter. IEEE J. Solid State Circuits 31(12): 2030-2035 (1996)
Coauthor Index
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