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Francesco Lorenzelli
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2020 – today
- 2024
- [c7]Tsung-Hsuan Wang, Po-Yao Chuang, Francesco Lorenzelli
, Erik Jan Marinissen:
Test and Repair Improvements for UCIe. ETS 2024: 1-6 - 2023
- [c6]Po-Yao Chuang
Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages. 3DIC 2023: 1-6 - [c5]Francesco Lorenzelli
Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications. ETS 2023: 1-6 - [c4]Francesco Lorenzelli
Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures. ITC 2023: 151-158 - [c3]Po-Yao Chuang
Generating Test Patterns for Chiplet Interconnects: Achieving Optimal Effectiveness and Efficiency. ITC-Asia 2023: 1-6 - [c2]Po-Yao Chuang
Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages. VTS 2023: 1-6 - 2021
- [c1]Francesco Lorenzelli
Speeding up Cell-Aware Library Characterization by Preceding Simulation with Structural Analysis. ETS 2021: 1-6
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last updated on 2024-10-07 21:25 CEST by the dblp team
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