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Andriy Hikavyy
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2020 – today
- 2023
- [c7]A. Elsayed, Clement Godfrin, Nard I. Dumoulin Stuyck, M. M. K. Shehata, Stefan Kubicek, S. Massar, Yann Canvel, Julien Jussot, Andriy Hikavyy, Roger Loo
, George Simion, Massimo Mongillo, D. Wan, Bogdan Govoreanu, R. Li
Comprehensive 300 mm process for Silicon spin qubits with modular integration. VLSI Technology and Circuits 2023: 1-2 - [c6]Hans Mertens, M. Hosseini, Thomas Chiarella, D. Zhou, S. Wang, G. Mannaert, E. Dupuy, D. Radisic, Z. Tao, Yusuke Oniki, Andriy Hikavyy, R. Rosseel, A. Mingardi, S. Choudhury, P. Puttarame Gowda, F. Sebaai, A. Peter, Kevin Vandersmissen, J. P. Soulie, An De Keersgieter, L. Petersen Barbosa Lima, C. Cavalcante, D. Batuk, G. T. Martinez, J. Geypen, F. Seidel, K. Paulussen, P. Favia, Jürgen Bömmels, Roger Loo
Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c5]Anabela Veloso, Geert Eneman, An De Keersgieter, P. Favia, Andriy Hikavyy, Rongmei Chen, Anne Jourdain, N. Horiguchi:
Innovations in Transistor Architecture and Device Connectivity for Advanced Logic Scaling. ICICDT 2022: 51-54 - [c4]Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher
Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails. VLSI Technology and Circuits 2022: 284-285 - [c3]A. Vandooren, N. Parihar, Jacopo Franco, Roger Loo
Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections. VLSI Technology and Circuits 2022: 330-331
2010 – 2019
- 2018
- [j1]Shimpei Yamaguchi, Liesbeth Witters, Jérôme Mitard, Geert Eneman, Geert Hellings, Andriy Hikavyy, Roger Loo
Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET. Microelectron. Reliab. 83: 157-161 (2018) - [c2]A. Vandooren, Liesbeth Witters, Jacopo Franco, Arindam Mallik, Bertrand Parvais
Sequential 3D: Key integration challenges and opportunities for advanced semiconductor scaling. ICICDT 2018: 145-148 - 2016
- [c1]Thomas Chiarella, Stefan Kubicek, E. Rosseel, Romain Ritzenthaler, Andriy Hikavyy, P. Eyben, An De Keersgieter, L.-Å. Ragnarsson, M.-S. Kim, S.-A. Chew, Tom Schram, S. Demuynck, Miroslav Cupák, Luc Rijnders, Morin Dehan, Naoto Horiguchi, Jérôme Mitard, Dan Mocuta, Anda Mocuta, Aaron Voon-Yew Thean:
Towards high performance sub-10nm finW bulk FinFET technology. ESSDERC 2016: 131-134
Coauthor Index
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