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Chi-An Wu
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2020 – today
- 2023
- [c16]Chung-Han Chou, Chih-Jen (Jacky) Hsu, Chi-An (Rocky) Wu, Kuan-Hua Tu, Kei-Yong Khoo:
Invited Paper: 2023 ICCAD CAD Contest Problem A: Multi-Bit Large-Scale Boolean Matching. ICCAD 2023: 1-4 - 2022
- [c15]Chung-Han Chou, Chih-Jen (Jacky) Hsu, Chi-An (Rocky) Wu, Kuan-Hua Tu:
2022 CAD Contest Problem A: Learning Arithmetic Operations from Gate-Level Circuit. ICCAD 2022: 93:1-93:4 - 2021
- [c14]Yen-Chun Fang, Shao-Lun Huang, Chi-An Wu, Chung-Han Chou, Chih-Jen Hsu, WoeiTzy Jong, Kei-Yong Khoo:
2021 CAD Contest Problem A: Functional ECO with Behavioral Change Guidance Invited Paper. ICCAD 2021: 1-6 - 2020
- [c13]Chih-Jen Hsu, Chi-An Wu, Ching-Yi Huang, Kei-Yong Khoo:
ICCAD-2020 CAD Contest in X-value Equivalence Checking and Benchmark Suite : Invited Talk. ICCAD 2020: 68:1-68:4
2010 – 2019
- 2019
- [c12]Ching-Yi Huang, Chi-An (Rocky) Wu, Tung-Yuan Lee, Chih-Jen (Jacky) Hsu, Kei-Yong Khoo:
2019 CAD Contest: Logic Regression on High Dimensional Boolean Space. ICCAD 2019: 1-6 - 2017
- [c11]Ching-Yi Huang, Chih-Jen Hsu, Chi-An Wu, Kei-Yong Khoo:
ICCAD-2017 CAD contest in resource-aware patch generation. ICCAD 2017: 857-862 - 2016
- [c10]Chi-An (Rocky) Wu, Chih-Jen (Jacky) Hsu, Kei-Yong Khoo:
ICCAD-2016 CAD contest in non-exact projective NPNP boolean matching and benchmark suite. ICCAD 2016: 40 - 2015
- [c9]Chih-Jen Hsu, Chi-An Wu, Wei-Hsun Lin, Kei-Yong Khoo:
ICCAD-2015 CAD Contest in Large-scale Equivalence Checking and Function Correction and Benchmark Suite. ICCAD 2015: 916-920 - 2014
- [j1]Cheng-Yin Wu, Chi-An Wu, Chien-Yu Lai, Chung-Yang (Ric) Huang:
A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1846-1858 (2014) - [c8]Chih-Jen Hsu, Wei-Hsun Lin, Chi-An Wu, Kei-Yong Khoo:
ICCAD-2014 CAD contest in simultaneous CNF encoder optimization with SAT solver setting selection and benchmark suite. ICCAD 2014: 357-360 - 2013
- [c7]Cheng-Yin Wu, Chi-An Wu, Chien-Yu Lai, Chung-Yang (Ric) Huang:
A counterexample-guided interpolant generation algorithm for SAT-based model checking. DAC 2013: 118:1-118:6 - 2011
- [c6]Shao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu, Chung-Yang Huang:
A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimization. ASP-DAC 2011: 382-387 - [c5]Kai-Fu Tang, Chi-An Wu, Po-Kai Huang, Chung-Yang (Ric) Huang:
Interpolation-based incremental ECO synthesis for multi-error logic rectification. DAC 2011: 146-151 - [c4]Yu-Fu Yeh, Chung-Yang Huang, Chi-An Wu, Hsin-Cheng Lin:
Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method. DATE 2011: 353-358
2000 – 2009
- 2009
- [c3]Chi-An Wu, Ting-Hao Lin, Shao-Lun Huang, Chung-Yang Huang:
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique. ASP-DAC 2009: 191-196 - [c2]Chih-Jen Hsu, Shao-Lun Huang, Chi-An Wu, Chung-Yang Huang:
Interpolant generation without constructing resolution graph. ICCAD 2009: 9-12 - 2007
- [c1]Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee, Chung-Yang Huang:
QuteSAT: a robust circuit-based SAT solver for complex circuit structure. DATE 2007: 1313-1318
Coauthor Index
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