research-article

SAT-controlled redundancy addition and removal: a novel circuit restructuring technique

Authors:

Shao-Lun Huang,

Chung-Yang Ric HuangAuthors Info & Claims

ASP-DAC '09: Proceedings of the 2009 Asia and South Pacific Design Automation Conference

Pages 191 - 196

Published: 19 January 2009 Publication History

Abstract

We proposed a novel Boolean Satisfiability (SAT)-controlled redundancy addition and removal (RAR) algorithm to resolve the performance and quality problems of the previous RAR approaches. With the introduction of modern SAT techniques, such as efficient Boolean constraint propagation (BCP), conflict-driven learning, and flexible decision procedure, our RAR engine can identify 10x more alternative wires/gates while achieving 70% reduction in runtime.

References

[1]

L. A. Entrena and K.-T. Cheng, "Combinational and Sequential logic Optimization by Redundancy Addition and Removal," in IEEE TCAD. vol. 14, no. 7, pp. 909--916, July 1995.

Digital Library

[2]

C-Y. Huang, Y. Wang, and K.-T. Cheng, "Libra - A Library-Independent Framework for Post-Layout Performance Optimization," in ISPD, pp. 135--140, Apr. 1998.

Digital Library

[3]

S-Y. Huang and K-T. Cheng, "Formal Equivalence Checking and Design Debugging," Kluwer Academic Publishers, 1998.

Digital Library

[4]

C.-C. Lin, K.-C. Chen and M. Marek-Sadowska, "Logic Synthesis for Engineering Change," in IEEE TCAD, Mar. 1999.

Digital Library

[5]

S. C. Chang, K.-T. Cheng, N.-S. Woo, and M. Marek-Sadowska, "Layout driven logic synthesis for FPGA," in Proc DAC, 1994.

Digital Library

[6]

R. Bahar, M. Burns, G. Hachtel, E. Macii, H. Shin, F. Somenzi, "Symbolic Computation of Logic Implications for Technology-Dependent Low-Power Synthesis," in Proc ISSLPED, 1996.

Digital Library

[7]

S.-C. Chang, M. Marek-Sadowska and K.-T. Cheng, "Perturb and Simplify: Multilevel Boolean Network Optimizer," in IEEE TCAD, vol. 15, no. 12, pp 1494--1504, Dec. 1996.

Digital Library

[8]

L. A. Entrena, J. A. Espejo, E. Olias and J. Uceda, "Timing Optimization by an Improved Redundancy Addition and Removal Technique," in Proceedings of EURO-DAC, 1996.

Digital Library

[9]

C-W (Jim) Chang and M. Marek-Sadowska, "Single-Pass Redundancy Addition And Removal," in Proc. ICCAD, 2001.

Digital Library

[10]

M. A. Iyer and M. Abramovici, "FIRE: A Fault-Independent Combinational Redundancy Identification Algorithm," in IEEE Trans. on VLSI, vol. 4, pp. 295--301, June 1996.

Digital Library

[11]

M. Abranovici, M. A. Breuer, and A. D. Friedman, "Digital Systems Testing and Testable Design", Wiley Press, Rev. Ed, 1994.

[12]

Oscar H. Ibarra, Sartaj Sahni, "Polynomially Complete Fault Detection Problems," in IEEE TComp. vol. 24, no. 3, 1975.

Digital Library

[13]

W. C. Tang, W. H. Lo, T. K. Lam, K. K. Mok, C. K. Ho S. H. Yeung, H. B. Fan, and Y. L. Wu, "A Quantitative Comparison and Analysis on Rewiring Techniques," in Proceedings of International Conference on ASIC, vol. 1, pp. 242--245, Oct. 2003.

[14]

W. Kunz and D. K. Pradhan, "Recursive Learning: An Attractive Alternative to the Decision Tree, Test Generation in Digital Circuits," in Proc. of ITC, pp. 816--825, Oct. 1992.

Digital Library

[15]

C-A. Wu, T-H. Lin, C-C. Lee, and C-Y (Ric) Huang, "QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure", Proc. DATE, March 2007.

Digital Library

Cited By

Lam TTang WYang XWu Y(2012)ECRACM Transactions on Design Automation of Electronic Systems10.1145/2348839.234885417:4(1-21)Online publication date: 1-Oct-2012
https://dl.acm.org/doi/10.1145/2348839.2348854
Wan LChen DShanbhag NPoncino MChou PAmerasekera A(2012)CCPProceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design10.1145/2333660.2333695(135-140)Online publication date: 30-Jul-2012
https://dl.acm.org/doi/10.1145/2333660.2333695
Yang XLam TWu YSapatnekar S(2010)ECRProceedings of the 47th Design Automation Conference10.1145/1837274.1837400(511-516)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837400

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Information & Contributors

Information

Published In

cover image ACM Conferences

ASP-DAC '09: Proceedings of the 2009 Asia and South Pacific Design Automation Conference

January 2009

902 pages

ISBN:9781424427482

General Chair:
Kazutoshi Wakabayashi
NEC Corporation

Sponsors

IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IPSJ SIGSLDM: Information Processing Society of Japan - SIG System LSI Design Methodology
IEICE ESS: Institute of Electronics, Information and Communication Engineers - Engineering Sciences Society

Publisher

IEEE Press

Publication History

Published: 19 January 2009

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Research-article

Conference

ASPDAC '09

Sponsor:

SIGDA
IPSJ SIGSLDM
IEICE ESS

ASPDAC '09: Asia and South Pacific Design Automation Conference

January 19 - 22, 2009

Yokohama, Japan

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

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ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

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Cited By

Lam TTang WYang XWu Y(2012)ECRACM Transactions on Design Automation of Electronic Systems10.1145/2348839.234885417:4(1-21)Online publication date: 1-Oct-2012
https://dl.acm.org/doi/10.1145/2348839.2348854
Wan LChen DShanbhag NPoncino MChou PAmerasekera A(2012)CCPProceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design10.1145/2333660.2333695(135-140)Online publication date: 30-Jul-2012
https://dl.acm.org/doi/10.1145/2333660.2333695
Yang XLam TWu YSapatnekar S(2010)ECRProceedings of the 47th Design Automation Conference10.1145/1837274.1837400(511-516)Online publication date: 13-Jun-2010
https://dl.acm.org/doi/10.1145/1837274.1837400

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