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Chung-Han Chou
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2020 – today
- 2023
- [c9]Chung-Han Chou, Chih-Jen (Jacky) Hsu, Chi-An (Rocky) Wu, Kuan-Hua Tu, Kei-Yong Khoo:
Invited Paper: 2023 ICCAD CAD Contest Problem A: Multi-Bit Large-Scale Boolean Matching. ICCAD 2023: 1-4 - 2022
- [c8]Chung-Han Chou, Chih-Jen (Jacky) Hsu, Chi-An (Rocky) Wu, Kuan-Hua Tu:
2022 CAD Contest Problem A: Learning Arithmetic Operations from Gate-Level Circuit. ICCAD 2022: 93:1-93:4 - 2021
- [c7]Yen-Chun Fang, Shao-Lun Huang, Chi-An Wu, Chung-Han Chou, Chih-Jen Hsu, WoeiTzy Jong, Kei-Yong Khoo:
2021 CAD Contest Problem A: Functional ECO with Behavioral Change Guidance Invited Paper. ICCAD 2021: 1-6 - 2020
- [j4]Tien-Hung Tseng, Chung-Han Chou, Kai-Chiang Wu:
Making Aging Useful by Recycling Aging-induced Clock Skew. ACM Trans. Design Autom. Electr. Syst. 25(2): 13:1-13:24 (2020)
2010 – 2019
- 2019
- [c6]Yun-Ting Wang, Kai-Chiang Wu, Chung-Han Chou, Shih-Chieh Chang:
Aging-aware chip health prediction adopting an innovative monitoring strategy. ASP-DAC 2019: 179-184 - 2018
- [j3]Chung-Han Chou
, Tsui-Yun Chang, Kai-Chiang Wu, Shih-Chieh Chang:
Sensor-Based Time Speculation in the Presence of Timing Variability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1133-1142 (2018) - 2017
- [j2]Chung-Han Chou
Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 146-155 (2017) - [c5]Kassan Unda, Chung-Han Chou, Shih-Chieh Chang, Cheng Zhuo, Yiyu Shi:
CN-SIM: A cycle-accurate full system power delivery noise simulator. ASP-DAC 2017: 554-559 - 2016
- [j1]Chung-Han Chou, Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh, Shih-Chieh Chang, Yung-Tai Chang:
Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1189-1192 (2016) - 2013
- [c4]Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou:
Low-power timing closure methodology for ultra-low voltage designs. ICCAD 2013: 697-704 - [c3]Chung-Han Chou, Nien-Yu Tsai, Hao Yu, Yiyu Shi, Jui-Hung Chien, Shih-Chieh Chang:
On the futility of thermal through-silicon-vias. VLSI-DAT 2013: 1-6 - 2011
- [c2]Chung-Han Chou, Nien-Yu Tsai, Hao Yu, Che-Rung Lee, Yiyu Shi, Shih-Chieh Chang:
On the preconditioner of conjugate gradient method - A power grid simulation perspective. ICCAD 2011: 494-497 - 2010
- [c1]Chiao-Ling Lung, Zi-Yi Zeng, Chung-Han Chou, Shih-Chieh Chang:
Clock skew optimization considering complicated power modes. DATE 2010: 1474-1479
Coauthor Index
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