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Kei-Yong Khoo
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2020 – today
- 2023
- [c34]Chung-Han Chou, Chih-Jen (Jacky) Hsu, Chi-An (Rocky) Wu, Kuan-Hua Tu, Kei-Yong Khoo:
Invited Paper: 2023 ICCAD CAD Contest Problem A: Multi-Bit Large-Scale Boolean Matching. ICCAD 2023: 1-4 - 2021
- [c33]Yen-Chun Fang, Shao-Lun Huang, Chi-An Wu, Chung-Han Chou, Chih-Jen Hsu, WoeiTzy Jong, Kei-Yong Khoo:
2021 CAD Contest Problem A: Functional ECO with Behavioral Change Guidance Invited Paper. ICCAD 2021: 1-6 - 2020
- [c32]Chih-Jen Hsu, Chi-An Wu, Ching-Yi Huang, Kei-Yong Khoo:
ICCAD-2020 CAD Contest in X-value Equivalence Checking and Benchmark Suite : Invited Talk. ICCAD 2020: 68:1-68:4
2010 – 2019
- 2019
- [c31]Ching-Yi Huang, Chi-An (Rocky) Wu, Tung-Yuan Lee, Chih-Jen (Jacky) Hsu, Kei-Yong Khoo:
2019 CAD Contest: Logic Regression on High Dimensional Boolean Space. ICCAD 2019: 1-6 - 2017
- [c30]Ching-Yi Huang, Chih-Jen Hsu, Chi-An Wu, Kei-Yong Khoo:
ICCAD-2017 CAD contest in resource-aware patch generation. ICCAD 2017: 857-862 - 2016
- [c29]Chi-An (Rocky) Wu, Chih-Jen (Jacky) Hsu, Kei-Yong Khoo:
ICCAD-2016 CAD contest in non-exact projective NPNP boolean matching and benchmark suite. ICCAD 2016: 40 - 2015
- [c28]Yu-Yun Dai, Kei-Yong Khoo, Robert K. Brayton:
Sequential equivalence checking of clock-gated circuits. DAC 2015: 51:1-51:6 - [c27]Chih-Jen Hsu, Chi-An Wu, Wei-Hsun Lin, Kei-Yong Khoo:
ICCAD-2015 CAD Contest in Large-scale Equivalence Checking and Function Correction and Benchmark Suite. ICCAD 2015: 916-920 - 2014
- [c26]Chih-Jen Hsu, Wei-Hsun Lin, Chi-An Wu, Kei-Yong Khoo:
ICCAD-2014 CAD contest in simultaneous CNF encoder optimization with SAT solver setting selection and benchmark suite. ICCAD 2014: 357-360 - 2013
- [c25]Chih-Jen Hsu, Wei-Hsun Lin, Hwei-Tseng Wang, Feng Lu, Kei-Yong Khoo:
ICCAD-2013 CAD contest in technology mapping for macro blocks and benchmark suite. ICCAD 2013: 265-267 - 2012
- [c24]WoeiTzy Jong, Hwei-Tseng Wang, Chengta Hsieh, Kei-Yong Khoo:
ICCAD-2012 CAD contest in finding the minimal logic difference for functional ECO and benchmark suite: CAD contest. ICCAD 2012: 342-344
2000 – 2009
- 2008
- [c23]Chao-Yue Lai, Chung-Yang Huang, Kei-Yong Khoo:
Improving Constant-Coefficient Multiplier Verification by Partial Product Identification. DATE 2008: 813-818 - 2006
- [c22]Kei-Yong Khoo:
Formal Verifications in Modern Chip Designs. HLDVT 2006: 38 - 2005
- [c21]Kei-Yong Khoo, Alan N. Willson Jr.:
Efficient VLSI implementation of N/N integer division. ISCAS (1) 2005: 672-675 - 2003
- [j5]Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.:
Optimal joint module-selection and retiming with carry-save representation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7): 836-846 (2003) - 2001
- [j4]Jason Cong, Jie Fang, Kei-Yong Khoo:
DUNE-a multilayer gridless routing system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5): 633-647 (2001) - [c20]Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.:
Design of optimal hybrid form FIR filter. ISCAS (2) 2001: 621-624 - 2000
- [j3]Jason Cong, Jie Fang, Kei-Yong Khoo:
Via design rule consideration in multilayer maze routing algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2): 215-223 (2000) - [c19]Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.:
The use of carry-save representation in joint module selection and retiming. DAC 2000: 768-773 - [c18]Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.:
Efficient implementation of FIR filters using bit-level optimized carry-save additions. EUSIPCO 2000: 1-4 - [c17]Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.:
Joint module selection and retiming with carry-save representation. EUSIPCO 2000: 1-4 - [c16]Jason Cong, Jie Fang, Kei-Yong Khoo:
DUNE: a multi-layer gridless routing system with wire planning. ISPD 2000: 12-18
1990 – 1999
- 1999
- [c15]Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.:
Bit-level arithmetic optimization for carry-save additions. ICCAD 1999: 14-19 - [c14]Jason Cong, Jie Fang, Kei-Yong Khoo:
An implicit connection graph maze routing algorithm for ECO routing. ICCAD 1999: 163-167 - [c13]Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.:
Improved-Booth encoding for low-power multipliers. ISCAS (1) 1999: 62-65 - [c12]Kei-Yong Khoo, Chao-Liang Chen, Alan N. Willson Jr.:
A CMOS pipelined carry-save array using true single-phase single-transistor-latch clocking. ISCAS (1) 1999: 298-301 - [c11]Jason Cong, Jie Fang, Kei-Yong Khoo:
VIA design rule consideration in multi-layer maze routing algorithms. ISPD 1999: 214-220 - 1997
- [c10]Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo:
Interconnect design for deep submicron ICs. ICCAD 1997: 478-485 - 1996
- [j2]Kei-Yong Khoo, Alan Y. Kwentus, Alan N. Willson Jr.:
A programmable FIR digital filter using CSD coefficients. IEEE J. Solid State Circuits 31(6): 869-874 (1996) - [c9]Kei-Yong Khoo, Alan N. Willson Jr.:
Cycle-Based Timing Simulations Using Event-Stream. ICCD 1996: 460-465 - 1995
- [j1]Kei-Yong Khoo, Jason Cong:
An efficient multilayer MCM router based on four-via routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(10): 1277-1290 (1995) - [c8]Kei-Yong Khoo, Alan N. Willson Jr.:
Single-transistor transparent-latch clocking. ARVLSI 1995: 331-341 - [c7]Chao-Liang Chen, Kei-Yong Khoo, Alan N. Willson Jr.:
An Improved Polynomial-Time Algorithm for Designing Digital Filters with Power-of-Two Coefficients. ISCAS 1995: 223-226 - [c6]Kei-Yong Khoo, Alan N. Willson Jr.:
Charge recovery on a databus. ISLPD 1995: 185-189 - 1994
- [c5]Kei-Yong Khoo, Alan N. Willson Jr.:
Low Power CMOS Clock Buffer. ISCAS 1994: 355-358 - 1993
- [c4]Kei-Yong Khoo, Jason Cong:
An Efficient Multilayer MCM Router Based on Four-Via Routing. DAC 1993: 590-595 - [c3]Kei-Yong Khoo, Alan Y. Kwentus, Alan N. Willson Jr.:
An efficient 175 MHz programmable FIR digital filter. ISCAS 1993: 72-75 - 1992
- [c2]Kei-Yong Khoo, Jason Cong:
A fast multilayer general area router for MCM designs. EURO-DAC 1992: 292-297 - 1991
- [c1]Jason Cong, Kei-Yong Khoo:
A Provable Near-Optimal Algorithm for the Channel Pin Assignment Problem. ICCD 1991: 319-322
Coauthor Index
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