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Geir Eide
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2020 – today
- 2021
- [c7]Yu Huang, Haitao Fu, Bin Deng, Edward Seng, Marc Hutner, Jean-Francois Cote, Geir Eide:
The Advancement of 1149.10. ITC-Asia 2021: 1 - 2020
- [c6]Jean-François Côté, Mark Kassab, Wojciech Janiszewski, Ricardo Rodrigues, Reinhard Meier, Bartosz Kaczmarek, Peter Orlando, Geir Eide, Janusz Rajski, Glenn Colón-Bonet, Naveen Mysore, Ya Yin, Pankaj Pant:
Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs. ITC 2020: 1-10
2010 – 2019
- 2017
- [c5]Wu-Tung Cheng, Randy Klingenberg, Brady Benware, Wu Yang, Manish Sharma, Geir Eide, Yue Tian, Sudhakar M. Reddy, Yan Pan, Sherwin Fernandes, Atul Chittora:
Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data. ATS 2017: 219-224 - 2013
- [j3]Shobhit Malik, Thomas Herrmann, Sriram Madhavan
, Rao Desineni, Chris Schuermyer, Geir Eide:
Deriving Feature Fail Rate from Silicon Volume Diagnostics Data. IEEE Des. Test 30(4): 26-34 (2013) - 2012
- [j2]Markus Seuring, Michael Braun, Alan Ma, Geir Eide, Kathy Yang, Huaxing Tang:
Employing the STDF V4-2007 Standard for Scan Test Data Logging. IEEE Des. Test 29(6): 91-99 (2012)
2000 – 2009
- 2004
- [j1]Carol Stolicny, Mustapha Slamani, Fidel Muradali, Geir Eide, Mike Li:
ITC 2003 panels: Part 2. IEEE Des. Test Comput. 21(3): 175-176, 261-262 (2004) - 2003
- [c4]Kenneth E. Posse, Geir Eide:
Key Impediments to DFT-Focused Test and How to Overcome Them. ITC 2003: 503-511 - [c3]Geir Eide, Kenneth E. Posse:
Open Microphone - My DFT is better than yours ... ITC 2003: 1285 - 2002
- [c2]Geir Eide:
Design-for-Test Techniques for SoC Designs (Tutorial Abstract). ISQED 2002: 7 - [c1]Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian:
Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC 2002: 301-310
Coauthor Index
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