research-article

Ultra-fast interconnect driven cell cloning for minimizing critical path delay

Authors:

Charles J. Alpert,

Ying ZhouAuthors Info & Claims

ISPD '10: Proceedings of the 19th international symposium on Physical design

Pages 75 - 82

https://doi.org/10.1145/1735023.1735047

Published: 14 March 2010 Publication History

Abstract

In a complete physical synthesis flow, optimization transforms, that can improve the timing on critical paths that are already well-optimized by a series of powerful transforms (timing driven placement, buffering and gate sizing) are invaluable. Finding such a transform is quite challenging, to say nothing of efficiency. This work explores innovative cloning (gate duplication) techniques to improve timing-closure in a physical synthesis environment.

With a buffer-aware interconnect timing model, new polynomial-time optimal algorithms are proposed for timing-driven cloning, including both finding optimal sink partitions (identifying the fan-outs) for the original and the duplicated gates, as well as physical locations for both gates. In particular, we present an O(m)-time optimal algorithm to minimize the worst slack if the original gate is movable, and an O(m log m) algorithm if the original gate is fixed, where $m$ is the number of fan-outs. To the best of our knowledge, this work is the first one considering the timing-driven cloning problem under a buffer-aware interconnect delay model.

For a hundred testcases in 45nm technology node, we demonstrate significant timing improvement due to our cloning techniques as compared to other existing timing-optimization transforms. Extensions to other factors, such as wirelength, FOM and placement obstacles are further discussed.

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Cited By

Marakkalage DDe Micheli G(2024)Fanout-Bounded Logic Synthesis for Emerging TechnologiesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.333944043:5(1415-1428)Online publication date: May-2024
https://doi.org/10.1109/TCAD.2023.3339440
Marakkalage DDe Micheli G(2023)Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137314(1-6)Online publication date: Apr-2023
https://doi.org/10.23919/DATE56975.2023.10137314
Zhang HJiang J(2020)SFO: A Scalable Approach to Fanout-Bounded Logic Synthesis for Emerging Technologies2020 57th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18072.2020.9218500(1-6)Online publication date: Jul-2020
https://doi.org/10.1109/DAC18072.2020.9218500
Show More Cited By

Index Terms

Ultra-fast interconnect driven cell cloning for minimizing critical path delay
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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Published In

cover image ACM Conferences

ISPD '10: Proceedings of the 19th international symposium on Physical design

March 2010

220 pages

ISBN:9781605589206

DOI:10.1145/1735023

General Chair:
Prashant Saxena
Synopsys
,
Program Chair:
Yao-Wen Chang
National Taiwan University

Copyright © 2010 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 14 March 2010

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ISPD '10: International Symposium on Physical Design

March 14 - 17, 2010

California, San Francisco, USA

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ISPD '10 Paper Acceptance Rate 22 of 70 submissions, 31%;

Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

Marakkalage DDe Micheli G(2024)Fanout-Bounded Logic Synthesis for Emerging TechnologiesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.333944043:5(1415-1428)Online publication date: May-2024
https://doi.org/10.1109/TCAD.2023.3339440
Marakkalage DDe Micheli G(2023)Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137314(1-6)Online publication date: Apr-2023
https://doi.org/10.23919/DATE56975.2023.10137314
Zhang HJiang J(2020)SFO: A Scalable Approach to Fanout-Bounded Logic Synthesis for Emerging Technologies2020 57th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC18072.2020.9218500(1-6)Online publication date: Jul-2020
https://doi.org/10.1109/DAC18072.2020.9218500
Jung JNam GChung WShin Y(2019)Integrated Latch Placement and Cloning for Timing OptimizationACM Transactions on Design Automation of Electronic Systems10.1145/330161324:2(1-17)Online publication date: 9-Feb-2019
https://dl.acm.org/doi/10.1145/3301613
Li ZZhou YShi W(2012)$O(mn)$ Time Algorithm for Optimal Buffer Insertion of Nets With $m$ SinksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2011.217463931:3(437-441)Online publication date: 1-Mar-2012
https://dl.acm.org/doi/10.1109/TCAD.2011.2174639
Papa DMarkov IA. Papa DL. Markov I(2012)ConclusionsMulti-Objective Optimization in Physical Synthesis of Integrated Circuits10.1007/978-1-4614-1356-1_10(149-155)Online publication date: 8-Aug-2012
https://doi.org/10.1007/978-1-4614-1356-1_10

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