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David H. Albonesi
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- affiliation: Cornell University, Ithaca, NY, USA
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2020 – today
- 2020
- [c59]Nitish Kumar Srivastava, Hanchen Jin, Shaden Smith, Hongbo Rong, David H. Albonesi, Zhiru Zhang
:
Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations. HPCA 2020: 689-702 - [c58]Neeraj Kulkarni, Gonzalo Gonzalez-Pumariega, Amulya Khurana, Christine A. Shoemaker
CuttleSys: Data-Driven Resource Management for Interactive Services on Reconfigurable Multicores. MICRO 2020: 650-664 - [c57]Nitish Kumar Srivastava, Hanchen Jin, Jie Liu
MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product. MICRO 2020: 766-780 - [i1]Neeraj Kulkarni, Gonzalo Gonzalez-Pumariega, Amulya Khurana, Christine A. Shoemaker, Christina Delimitrou, David H. Albonesi:
CuttleSys: Data-Driven Resource Management forInteractive Applications on Reconfigurable Multicores. CoRR abs/2008.00329 (2020)
2010 – 2019
- 2019
- [c56]Nitish Kumar Srivastava, Hongbo Rong, Prithayan Barua, Guanyu Feng, Huanqi Cao, Zhiru Zhang
T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations. FCCM 2019: 181-189 - 2017
- [c55]Abhinandan Majumdar, Leonardo Piga, Indrani Paul
Dynamic GPGPU Power Management Using Adaptive Model Predictive Control. HPCA 2017: 613-624 - [c54]Tayyar Rzayev, Saber Moradi
DeepRecon: Dynamically reconfigurable architecture for accelerating deep neural networks. IJCNN 2017: 116-124 - [c53]Tayyar Rzayev, David H. Albonesi, François Guimbretière, Rajit Manohar, Jaeyeon Kihm:
Toolbox for exploration of energy-efficient event processors for human-computer interaction. ISPASS 2017: 173-184 - 2016
- [j27]David H. Albonesi:
2015 International Symposium on Computer Architecture Influential Paper Award. IEEE Micro 36(6): 60-61 (2016) - [c52]Abhinandan Majumdar, Zhiru Zhang
Characterizing the Benefits and Limitations of Smart Building Meeting Room Scheduling. ICCPS 2016: 6:1-6:10 - 2015
- [e2]Deborah T. Marr, David H. Albonesi:
Proceedings of the 42nd Annual International Symposium on Computer Architecture, Portland, OR, USA, June 13-17, 2015. ACM 2015, ISBN 978-1-4503-3402-0 [contents] - 2014
- [c51]Abhinandan Majumdar, Jason L. Setter, Justin R. Dobbs, Brandon M. Hencey, David H. Albonesi:
Energy-comfort optimization using discomfort history and probabilistic occupancy prediction. IGCC 2014: 1-10 - 2013
- [c50]Paula Petrica, Adam M. Izraelevitz, David H. Albonesi, Christine A. Shoemaker
Flicker: a dynamically adaptive architecture for power limited multicore systems. ISCA 2013: 13-23 - 2012
- [c49]Abhinandan Majumdar, David H. Albonesi, Pradip Bose:
Energy-aware meeting scheduling algorithms for smart buildings. BuildSys@SenSys 2012: 161-168 - 2011
- [j26]Mark J. Cianchetti, David H. Albonesi:
A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors. ACM J. Emerg. Technol. Comput. Syst. 7(2): 9:1-9:20 (2011) - [j25]Sonia López, Oscar Garnica
A phase adaptive cache hierarchy for SMT processors. Microprocess. Microsystems 35(8): 683-694 (2011) - [j24]Matthew A. Watkins, David H. Albonesi:
ReMAP: A Reconfigurable Architecture for Chip Multiprocessors. IEEE Micro 31(1): 65-77 (2011) - 2010
- [j23]David H. Albonesi:
Future Directions in Computer Architecture Research. IEEE Micro 30(3): 5 (2010) - [j22]David H. Albonesi:
Moving Forward. IEEE Micro 30(6): 4-5 (2010) - [c48]Jonathan A. Winter, David H. Albonesi, Christine A. Shoemaker
Scalable thread scheduling and global power management for heterogeneous many-core architectures. PACT 2010: 29-40 - [c47]Matthew A. Watkins, David H. Albonesi:
Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors. PACT 2010: 41-52 - [c46]Sonia López, Oscar Garnica
Adaptive Cache Memories for SMT Processors. DSD 2010: 331-338 - [c45]Matthew A. Watkins, David H. Albonesi:
ReMAP: A Reconfigurable Heterogeneous Multicore Architecture. MICRO 2010: 497-508
2000 – 2009
- 2009
- [j21]David H. Albonesi:
From the Editor in Chief: Welcome A-Board. IEEE Micro 29(5): 2-5 (2009) - [c44]Mark J. Cianchetti, Joseph C. Kerekes, David H. Albonesi:
Phastlane: a rapid transit optical routing network. ISCA 2009: 441-450 - [e1]David H. Albonesi, Margaret Martonosi, David I. August, José F. Martínez:
42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA. ACM 2009, ISBN 978-1-60558-798-1 [contents] - 2008
- [j20]David H. Albonesi:
Changes Ahead. IEEE Micro 28(5): 4 (2008) - [j19]Jonathan A. Winter, David H. Albonesi:
Addressing thermal nonuniformity in SMT workloads. ACM Trans. Archit. Code Optim. 5(1): 4:1-4:28 (2008) - [c43]Jonathan A. Winter, David H. Albonesi:
Scheduling algorithms for unpredictably heterogeneous CMP architectures. DSN 2008: 42-51 - [c42]Matthew A. Watkins, Mark J. Cianchetti, David H. Albonesi:
Shared reconfigurable architectures for CMPS. FPL 2008: 299-304 - 2007
- [j18]Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman:
Predictions of CMOS compatible on-chip optical interconnect. Integr. 40(4): 434-446 (2007) - [j17]David H. Albonesi:
Standing on Solid Ground. IEEE Micro 27(1): 5-6 (2007) - [j16]Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez
On-Chip Optical Technology in Future Bus-Based Multicore Designs. IEEE Micro 27(1): 56-66 (2007) - [j15]David H. Albonesi:
Editor in Chief's Message: Truly "hot" chips - Do we still care? IEEE Micro 27(2): 4-5 (2007) - [j14]David H. Albonesi:
More Hot Stuff. IEEE Micro 27(3): 4-5 (2007) - [j13]David H. Albonesi:
Mixing It Up. IEEE Micro 27(4): 3-4 (2007) - [j12]David H. Albonesi:
Productive and Healthy Debate. IEEE Micro 27(6): 6 (2007) - [c41]Sonia López, Steven G. Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares:
Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors. PACT 2007: 416 - [c40]Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. HiPEAC 2007: 136-150 - [c39]Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman:
On-chip optical interconnect for reduced delay uncertainty. Nano-Net 2007: 22 - 2006
- [c38]Ali El-Moursy
Compatible phase co-scheduling on a CMP of multi-threaded processors. IPDPS 2006 - [c37]Yongkang Zhu, David H. Albonesi:
Localized microarchitecture-level voltage management. ISCAS 2006 - [c36]Yongkang Zhu, David H. Albonesi:
Synergistic temperature and energy management in GALS processor architectures. ISLPED 2006: 55-60 - [c35]Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors. MICRO 2006: 492-503 - 2005
- [j11]M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang
Power-Efficient Error Tolerance in Chip Multiprocessors. IEEE Micro 25(6): 60-70 (2005) - [c34]M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang
Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance. IEEE PACT 2005: 315-328 - [c33]Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi:
Electrical and optical on-chip interconnects in scaled microprocessors. ISCAS (3) 2005: 2514-2517 - [c32]Yongkang Zhu, David H. Albonesi, Alper Buyuktosunoglu:
A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity. ISPASS 2005: 42-53 - [c31]Ali El-Moursy
Partitioning Multi-Threaded Processors with a Large Number of Threads. ISPASS 2005: 112-123 - [c30]Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi:
Predictions of CMOS compatible on-chip optical interconnect. SLIP 2005: 13-20 - [c29]Gregory J. Briggs, Edwin J. Tan, Nicholas A. Nelson, David H. Albonesi:
QUILT: a GUI-based integrated circuit floorplanning environment for computer architecture research and education. WCAE@ISCA 2005: 5 - 2004
- [j10]Wanli Liu, David H. Albonesi, John Gostomski, Lloyd Palum, Dave Hinterberger, Rick Wanzenried, Mark Indovina:
An Evaluation of a Configurable Vliw Microarchitecture for Embedded Dsp Applications. J. Circuits Syst. Comput. 13(6): 1321-1346 (2004) - [j9]David H. Albonesi:
Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences. IEEE Micro 24(6): 8-9 (2004) - [c28]Yongkang Zhu, Grigorios Magklis, Michael L. Scott, Chen Ding, David H. Albonesi:
The Energy Impact of Aggressive Loop Fusion. IEEE PACT 2004: 153-164 - [c27]Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott
Hiding Synchronization Delays in a GALS Processor Microarchitecture. ASYNC 2004: 159-169 - [c26]Steven G. Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott
Dynamically Trading Frequency for Complexity in a GALS Microprocessor. MICRO 2004: 157-168 - 2003
- [j8]David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas
Dynamically Tuning Processor Resources with Adaptive Processing. Computer 36(12): 49-58 (2003) - [j7]Pradip Bose, David H. Albonesi, Diana Marculescu
Guest Editors' Introduction: Power and Complexity Aware Design. IEEE Micro 23(5): 8-11 (2003) - [j6]Grigorios Magklis, Greg Semeraro, David H. Albonesi, Steve Dropsho, Sandhya Dwarkadas
Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor. IEEE Micro 23(6): 62-68 (2003) - [j5]Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
A Dynamically Tunable Memory Hierarchy. IEEE Trans. Computers 52(10): 1243-1258 (2003) - [c25]Ali El-Moursy
Front-End Policies for Improved Issue Efficiency in SMT Processors. HPCA 2003: 31-40 - [c24]Lei Chen, Steve Dropsho, David H. Albonesi:
Dynamic Data Dependence Tracking and its Application to Branch Prediction. HPCA 2003: 65-76 - [c23]Grigorios Magklis, Michael L. Scott
Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor. ISCA 2003: 14-25 - [c22]Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose:
Energy Efficient Co-Adaptive Instruction Fetch and Issue. ISCA 2003: 147-156 - [c21]Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi:
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors. ISCA 2003: 275-286 - 2002
- [c20]Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. IEEE PACT 2002: 141-152 - [c19]Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas
Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. HPCA 2002: 29-42 - [c18]Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster:
Tradeoffs in power-efficient issue queue design. ISLPED 2002: 184-189 - [c17]Wael El-Essawy, David H. Albonesi, Balaram Sinharoy:
A microarchitectural-level step-power analysis tool. ISLPED 2002: 263-266 - [c16]Steve Dropsho, Volkan Kursun
Managing static leakage energy in microprocessor functional units. MICRO 2002: 321-332 - [c15]Greg Semeraro, David H. Albonesi, Steve Dropsho, Grigorios Magklis, Sandhya Dwarkadas
Dynamic frequency and voltage control for a multiple clock domain microarchitecture. MICRO 2002: 356-367 - [c14]Pradip Bose, David M. Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas:
Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. PACS 2002: 1-17 - 2001
- [c13]Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David M. Brooks, Pradip Bose, Peter W. Cook:
A circuit level implementation of an adaptive issue queue for power-aware microprocessors. ACM Great Lakes Symposium on VLSI 2001: 73-78 - [c12]Brian W. Curran, Mary Gifaldi, Jason Martin, Alper Buyuktosunoglu, Martin Margala, David H. Albonesi:
Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors. VLSI-SOC 2001: 289-300 - [c11]Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi:
Dynamically allocating processor resources between nearby and distant ILP. ISCA 2001: 26-37 - [c10]Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi:
Reducing the complexity of the register file in dynamic superscalar processors. MICRO 2001: 237-248 - 2000
- [j4]Bingxiong Xu, David H. Albonesi:
Runtime Reconfiguration Techniques for Efficient General-Purpose Computation. IEEE Des. Test Comput. 17(1): 42-52 (2000) - [j3]David H. Albonesi:
Selective Cache Ways: On-Demand Cache Resource Allocation. J. Instr. Level Parallelism 2 (2000) - [c9]Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. MICRO 2000: 245-257 - [c8]Alper Buyuktosunoglu, Stanley Schuster, David M. Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi:
An Adaptive Issue Queue for Reduced Power at High Performance. PACS 2000: 25-39
1990 – 1999
- 1999
- [j2]David H. Albonesi, Israel Koren:
STATS: A framework for microprocessor and system-level design space exploration. J. Syst. Archit. 45(12-13): 1097-1110 (1999) - [c7]David H. Albonesi:
An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures. VLSI 1999: 192-205 - [c6]David H. Albonesi:
Selective Cache Ways: On-Demand Cache Resource Allocation. MICRO 1999: 248-259 - 1998
- [c5]David H. Albonesi:
Dynamic IPC/Clock Rate Optimization. ISCA 1998: 282-292 - 1997
- [c4]David H. Albonesi, Israel Koren:
Improving the Memory Bandwidth of Highly-Integrated, Wide-Issue, Microprocessor-Based Systems. IEEE PACT 1997: 126-135 - 1996
- [j1]David H. Albonesi, Israel Koren:
A Mean Analysis Multiprocessor Model Incorporating Superscalar Processors and Latency Tolerating Techniques. Int. J. Parallel Program. 24(3): 235-264 (1996) - 1995
- [c3]David H. Albonesi, Israel Koren:
An analytical model of high performance superscalar-based multiprocessors. PACT 1995: 194-203 - [c2]David H. Albonesi, Israel Koren:
Architecture and technology tradeoffs in the design of next-generation multiprocessor servers. SPDP 1995: 174-181 - 1994
- [c1]David H. Albonesi, Israel Koren:
Tradeoffs in the Design of Single Chip Multiprocessors. IFIP PACT 1994: 25-34
Coauthor Index
Steven G. Dropsho
aka: Steve Dropsho
aka: Steve Dropsho
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