research-article

Flicker: a dynamically adaptive architecture for power limited multicore systems

Authors:

Adam M. Izraelevitz,

David H. Albonesi,

Christine A. ShoemakerAuthors Info & Claims

ISCA '13: Proceedings of the 40th Annual International Symposium on Computer Architecture

Pages 13 - 23

https://doi.org/10.1145/2485922.2485924

Published: 23 June 2013 Publication History

Abstract

Future microprocessors may become so power constrained that not all transistors will be able to be powered on at once. These systems will be required to nimbly adapt to changes in the chip power that is allocated to general-purpose cores and to specialized accelerators.

This paper presents Flicker, a general-purpose multicore architecture that dynamically adapts to varying and potentially stringent limits on allocated power. The Flicker core microarchitecture includes deconfigurable lanes--horizontal slices through the pipeline--that permit tailoring an individual core to the running application with lower overhead than microarchitecture-level adaptation, and greater flexibility than core-level power gating.

To exploit Flicker's flexible pipeline architecture, a new online multicore optimization algorithm combines reduced sampling techniques, application of response surface models to online optimization, and heuristic online search. The approach efficiently finds a near-global-optimum configuration of lanes without requiring offline training, microarchitecture state, or foreknowledge of the workload. At high power allocations, core-level gating is highly effective, and slightly outperforms Flicker overall. However, under stringent power constraints, Flicker significantly outperforms core-level gating, achieving an average 27% performance improvement.

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cover image ACM Other conferences

ISCA '13: Proceedings of the 40th Annual International Symposium on Computer Architecture

June 2013

686 pages

ISBN:9781450320795

DOI:10.1145/2485922

General Chair:
Avi Mendelson
Technion

ACM SIGARCH Computer Architecture News Volume 41, Issue 3
ICSA '13
June 2013
666 pages
ISSN:0163-5964
DOI:10.1145/2508148
Issue’s Table of Contents

Copyright © 2013 ACM.

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Published: 23 June 2013

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Division of Computing and Communication Foundations
Cornell Engineering Learning Initiatives
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Intel Corporation

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ISCA'13

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ISCA'13: The 40th Annual International Symposium on Computer Architecture

June 23 - 27, 2013

Tel-Aviv, Israel

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ISCA '13 Paper Acceptance Rate 56 of 288 submissions, 19%;

Overall Acceptance Rate 543 of 3,203 submissions, 17%

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Li XYan GLiu CLi XYan GLiu C(2023)Fault-Tolerant General Purposed ProcessorsBuilt-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design10.1007/978-981-19-8551-5_3(117-168)Online publication date: 2-Mar-2023
https://doi.org/10.1007/978-981-19-8551-5_3
Weston KJanfaza VTaur AMungra DKansal AZahran MMuzahid A(2023)Post-Silicon Customization Using Deep Neural NetworksArchitecture of Computing Systems10.1007/978-3-031-42785-5_9(120-136)Online publication date: 26-Aug-2023
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Chen WWang YXu YGao CHan YZhang L(2022)Amphis: Managing Reconfigurable Processor Architectures With Generative Adversarial LearningIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319798041:11(3993-4003)Online publication date: Nov-2022
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