Article

Tradeoffs in power-efficient issue queue design

Authors:

Alper Buyuktosunoglu,

David H. Albonesi,

Pradip Bose,

Peter W. Cook,

Stanley E. SchusterAuthors Info & Claims

ISLPED '02: Proceedings of the 2002 international symposium on Low power electronics and design

Pages 184 - 189

https://doi.org/10.1145/566408.566454

Published: 12 August 2002 Publication History

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Abstract

A major consumer of microprocessor power is the issue queue. Several microprocessors, including the Alpha 21264 and POWER4^TM, use a compacting latch-based issue queue design which has the advantage of simplicity of design and verification. The disadvantage of this structure, however, is its high power dissipation.In this paper, we explore different issue queue power optimization techniques that vary not only in their performance and power characteristics, but in how much they deviate from the baseline implementation. By developing and comparing techniques that build incrementally on the baseline design, as well as those that achieve higher power savings through a more significant redesign effort, we quantify the extra benefit the higher design cost techniques provide over their more straightforward counterparts.

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Cited By

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Maniatakos MMichael MMakris YMacii E(2013)AVF-driven parity optimization for MBU protection of in-core memory arraysProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485639(1480-1485)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485639
Küçük GGüney İPonomarev D(2013)Instruction Scheduling in MicroprocessorsAutomated Scheduling and Planning10.1007/978-3-642-39304-4_2(39-60)Online publication date: 2013
https://doi.org/10.1007/978-3-642-39304-4_2
Sethumadhavan SRoesner FEmer JBurger DKeckler S(2007)Late-bindingACM SIGARCH Computer Architecture News10.1145/1273440.125070535:2(347-357)Online publication date: 9-Jun-2007
https://dl.acm.org/doi/10.1145/1273440.1250705
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Index Terms

Tradeoffs in power-efficient issue queue design
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Reconfigurable computing
      2. Self-organizing autonomic computing

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Information & Contributors

Information

Published In

ISLPED '02: Proceedings of the 2002 international symposium on Low power electronics and design

August 2002

342 pages

ISBN:1581134754

DOI:10.1145/566408

General Chairs:
Vivek De
Intel Corporation
,
Mary Jane Irwin
Penn State University
,
Program Chairs:
Ingrid Verbauwhede
University of California, Los Angeles
,
Christian Piguet
CSEM

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 12 August 2002

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ISLPED02

Sponsor:

ISLPED02: International Symposium on Power Design and Electronics

August 12 - 14, 2002

California, Monterey, USA

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ISLPED '02 Paper Acceptance Rate 40 of 162 submissions, 25%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Maniatakos MMichael MMakris YMacii E(2013)AVF-driven parity optimization for MBU protection of in-core memory arraysProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485639(1480-1485)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485639
Küçük GGüney İPonomarev D(2013)Instruction Scheduling in MicroprocessorsAutomated Scheduling and Planning10.1007/978-3-642-39304-4_2(39-60)Online publication date: 2013
https://doi.org/10.1007/978-3-642-39304-4_2
Sethumadhavan SRoesner FEmer JBurger DKeckler S(2007)Late-bindingACM SIGARCH Computer Architecture News10.1145/1273440.125070535:2(347-357)Online publication date: 9-Jun-2007
https://dl.acm.org/doi/10.1145/1273440.1250705
Sethumadhavan SRoesner FEmer JBurger DKeckler STullsen DCalder B(2007)Late-bindingProceedings of the 34th annual international symposium on Computer architecture10.1145/1250662.1250705(347-357)Online publication date: 9-Jun-2007
https://dl.acm.org/doi/10.1145/1250662.1250705
Vivekanandham RAmrutur BGovindarajan REgan GMuraoka Y(2006)A scalable low power issue queue for large instruction window processorsProceedings of the 20th annual international conference on Supercomputing10.1145/1183401.1183427(167-176)Online publication date: 28-Jun-2006
https://dl.acm.org/doi/10.1145/1183401.1183427
Weinraub YWeiss S(2006)Power-aware out-of-order issue logic in high-performance microprocessorsMicroprocessors and Microsystems10.1016/j.micpro.2006.05.00130:7(457-467)Online publication date: Nov-2006
https://doi.org/10.1016/j.micpro.2006.05.001
Li YParikh DZhang YSankaranarayanan KStan MSkadron K(2004)State-Preserving vs. Non-State-Preserving Leakage Control in CachesProceedings of the conference on Design, automation and test in Europe - Volume 110.5555/968878.969046Online publication date: 16-Feb-2004
https://dl.acm.org/doi/10.5555/968878.969046
Latorre FGonzález JGonzález AFeautrier PGoodman JSeznec A(2004)Back-end assignment schemes for clustered multithreaded processorsProceedings of the 18th annual international conference on Supercomputing10.1145/1006209.1006254(316-325)Online publication date: 26-Jun-2004
https://dl.acm.org/doi/10.1145/1006209.1006254
Seng JTullsen D(2003)Exploring the potential of architecture-level power optimizationsProceedings of the Third international conference on Power - Aware Computer Systems10.1007/978-3-540-28641-7_10(132-147)Online publication date: 1-Dec-2003
https://dl.acm.org/doi/10.1007/978-3-540-28641-7_10

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