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Alexandre V. Bystrov
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2020 – today
- 2023
- [c43]Yujin Zheng, Alex Bystrov
, Alex Yakovlev:
A Rapid Reset 8-Transistor Physically Unclonable Function Utilising Power Gating. DATE 2023: 1-2
2010 – 2019
- 2019
- [c42]Stanislavs Golubcovs, Andrey Mokhov, Alex Bystrov
Generalised Asynchronous Arbiter. ACSD 2019: 3-12 - 2017
- [c41]Mohamed A. Abufalgha, Alex Bystrov
Derivation of the reliability metric for digital circuits. ETS 2017: 1-2 - [c40]Mohamed A. Abufalgha, Alex Bystrov
Design-time reliability evaluation for digital circuits. IOLTS 2017: 39-44 - 2015
- [c39]Harith Fakhrey, Said Boussakta, Rajesh Tiwari, Yasir Al-Mathehaji, Alex Bystrov
Location-dependent key management protocol for a WSN with a random selected cell reporter. ICC 2015: 6300-6305 - 2014
- [c38]Musa Al Yaman
FPGA design for dual-spectrum visual scene preparation in retinal prosthesis. EMBC 2014: 4691-4694 - 2013
- [j14]Alexandre V. Bystrov
Selected Articles from the IEEE LPonTR 2012 Workshop. J. Low Power Electron. 9(1): 118 (2013) - [c37]Musa Al Yaman
FPGA design of a pulse encoder for optoelectronic neural stimulation and recording arrays. BioCAS 2013: 190-193 - [c36]James Docherty, Alexandre V. Bystrov
Simulation Testing of a Real-Time Heuristic Scheduler with Automotive Benchmarks. UKSim 2013: 424-429 - [c35]Nick Rutter, Said Boussakta, Alex Bystrov
Assessment of the One-Dimensional Generalized New Mersenne Number Transform for Security Systems. VTC Spring 2013: 1-5 - 2012
- [j13]Frank P. Burns, Alexandre V. Bystrov
Design and security evaluation of balanced 1-of-n circuits. IET Comput. Digit. Tech. 6(2): 125-135 (2012) - [c34]Norhuzaimin Julai, Alexandre Yakovlev
Error detection and correction of single event upset (SEU) tolerant latch. IOLTS 2012: 1-6 - [c33]Chenxi Ni, Gordon Russell, Alex Bystrov
Statistical delay modelling of manufacturing process variations at system level. NEWCAS 2012: 133-136 - [c32]Julian P. Murphy, Máire O'Neill, Frank P. Burns, Alexandre V. Bystrov
Self-Timed Physically Unclonable Functions. NTMS 2012: 1-5 - [c31]Chenxi Ni, Ziyad Al Tarawneh, Gordon Russell, Alexandre V. Bystrov
Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level. PATMOS 2012: 11-20 - [c30]James Docherty, Alexandre V. Bystrov
Identification of Key Energy Harvesting Parameters through Monte Carlo Simulations. UKSim 2012: 486-490 - 2011
- [j12]Frank P. Burns, Alexandre V. Bystrov
Security Evaluation of Balanced 1-of- n Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(11): 2135-2139 (2011) - [c29]Abdullah Baz
Improving the Robustness of Self-timed SRAM to Variable Vdds. PATMOS 2011: 32-42 - 2010
- [j11]Alex Bystrov
Selected Peer-Reviewed Articles from the LPonTR 2009 Workshop. J. Low Power Electron. 6(2): 325 (2010) - [c28]Steffen Zeidler, Alexandre V. Bystrov
On-line testing of bundled-data asynchronous handshake protocols. IOLTS 2010: 261-267
2000 – 2009
- 2008
- [j10]Alex Bystrov
Selected Peer-Reviewed Articles from the LPonTR 2008 Workshop. J. Low Power Electron. 4(3): 372-373 (2008) - [j9]Valery A. Nepomniaschy, Victor S. Argirov, Dmitri M. Beloglazov, Alexandre V. Bystrov
Modeling and verification of the SDL-specified communication protocols using high-level Petri nets. Program. Comput. Softw. 34(6): 330-340 (2008) - [j8]Crescenzo D'Alessandro, Delong Shang, Alexandre V. Bystrov
Phase-Encoding for On-Chip Signalling. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(2): 535-545 (2008) - [c27]Crescenzo D'Alessandro, Alex Bystrov
Implementation of a phase-encoding signalling prototype chip. ESSCIRC 2008: 478-481 - 2007
- [j7]Danil Sokolov, Alexandre V. Bystrov
Direct Mapping of Low-Latency Asynchronous Controllers From STGs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 993-1009 (2007) - [j6]Delong Shang, Alexandre Yakovlev
Registers for Phase Difference Based Logic. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 720-724 (2007) - [c26]Crescenzo D'Alessandro, Andrey Mokhov, Alexandre V. Bystrov
Delay/Phase Regeneration Circuits. ASYNC 2007: 105-116 - [c25]Valery A. Nepomniaschy, Gennady I. Alekseev, Victor S. Argirov, Dmitri M. Beloglazov, Alexandre V. Bystrov
Application of Modified Coloured Petri Nets to Modeling and Verification of SDL Specified Communication Protocols. CSR 2007: 303-314 - [c24]K. T. Gardiner, Alexandre Yakovlev
A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits. IOLTS 2007: 223-230 - 2006
- [c23]Crescenzo D'Alessandro, Delong Shang, Alexandre V. Bystrov
Multiple-Rail Phase-Encoding for NoC. ASYNC 2006: 107-116 - [c22]Delong Shang, Alexandre Yakovlev
Low-Cost Online Testing of Asynchronous Handshakes. ETS 2006: 225-232 - [c21]Deepali Koppad
Online Testing by Protocol Decomposition. IOLTS 2006: 263-268 - 2005
- [j5]Danil Sokolov, Julian P. Murphy, Alexandre V. Bystrov
Design and Analysis of Dual-Rail Circuits for Security Applications. IEEE Trans. Computers 54(4): 449-460 (2005) - [c20]Delong Shang, Alexandre V. Bystrov
On-Line Testing of Globally Asynchronous Circuits. IOLTS 2005: 135-140 - [c19]Julian P. Murphy, Alexandre V. Bystrov
Power-Balanced Self Checking Circuits for Cryptographic Chips. IOLTS 2005: 157-162 - [c18]Crescenzo D'Alessandro, Delong Shang, Alexandre V. Bystrov
PSK Signalling on NoC Buses. PATMOS 2005: 286-296 - [c17]Deepali Koppad
Off-Line Testing of Asynchronous Circuits. VLSI Design 2005: 730-735 - 2004
- [j4]Alexandre Yakovlev
Design and Analysis of a Self-Timed Duplex Communication System. IEEE Trans. Computers 53(7): 798-814 (2004) - [c16]Danil Sokolov, Julian P. Murphy, Alexandre V. Bystrov
Improving the Security of Dual-Rail Circuits. CHES 2004: 282-297 - [c15]Delong Shang, Frank P. Burns, Alexandre V. Bystrov
A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits. PATMOS 2004: 471-480 - 2003
- [j3]D. J. Kinniment, Oleh V. Maevsky, Alexandre V. Bystrov
On-chip structures for timing measurement and test. Microprocess. Microsystems 27(9): 473-483 (2003) - [c14]Alexandre V. Bystrov
Low-Latency Contro Structures with Slack. ASYNC 2003: 164-173 - [c13]Agnes Madalinski, Alexandre V. Bystrov, Victor Khomenko, Alexandre Yakovlev:
Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design. DATE 2003: 10926-10931 - [c12]Danil Sokolov, Alexandre V. Bystrov, Alexandre Yakovlev:
STG Optimisation in the Direct Mapping of Asynchronous Circuits . DATE 2003: 10932-10939 - 2002
- [j2]David J. Kinniment, Alexandre V. Bystrov
Synchronization circuit performance. IEEE J. Solid State Circuits 37(2): 202-209 (2002) - [c11]Alexandre V. Bystrov, Alexandre Yakovlev:
Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment. ASYNC 2002: 127-136 - [c10]D. J. Kinniment, Oleh V. Maevsky, Gordon Russell, Alexandre Yakovlev, Alexandre V. Bystrov:
On-Chip Structures for Timing Measurements and Test. ASYNC 2002: 190-197 - [c9]Alexandre V. Bystrov, Maciej Koutny, Alexandre Yakovlev:
Visualization of Partial Order Models in VLSI Design Flow. DATE 2002: 1089 - [c8]Oleh V. Maevsky, D. J. Kinniment, Alexandre Yakovlev, Alexandre V. Bystrov
Analysis of the oscillation problem in tri-flops. ISCAS (1) 2002: 381-384 - [c7]Agnes Madalinski, Alexandre V. Bystrov, Alexandre Yakovlev:
Visualization of Coding Conflicts in Asynchronous Circuit Design. IWLS 2002: 155-160 - [c6]Alexandre V. Bystrov, Alexandre Yakovlev:
Synthesis of Asynchronous Circuits with Predictable Latency. IWLS 2002: 239-243 - 2001
- [j1]Valery A. Nepomniaschy, Gennady I. Alekseev, Alexandre V. Bystrov
Verification of Estelle-Specified Communication Protocols Using High-Level Petri Nets. Program. Comput. Softw. 27(2): 58-68 (2001) - 2000
- [c5]Alexandre V. Bystrov
Priority Arbiters. ASYNC 2000: 128-137 - [c4]Fei Xia, Alexandre Yakovlev
Asynchronous Communication Mechanisms Using Self-Timed Circuits. ASYNC 2000: 150- - [c3]Nikolai Starodoubtsev, Alexandre V. Bystrov
Semi-modular Latch Chains for Asynchronous Circuit Design. PATMOS 2000: 168-177
1990 – 1999
- 1999
- [c2]Alexandre V. Bystrov
Implementing Model Checking and Equivalence Checking for Time Petri Nets by the RT-MEC Tool. PaCT 1999: 194-199 - 1995
- [c1]Valery A. Nepomniaschy, Gennady I. Alekseev, Alexandre V. Bystrov, Tatiana G. Churina, Sergey P. Mylnikov, E. V. Okunishnikova:
Petri Net Modelling of Estelle-specified Communication Protocols. PaCT 1995: 94-108
Coauthor Index
aka: Alex Yakovlev
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