Improving the Robustness of Self-timed SRAM to Variable Vdds

1. Baz, A., Shang, D., Xia, F., Yakovlev, A.: Self-Timed SRAM for Energy Harvesting Systems. In: van Leuken, R., Sicard, G. (eds.) PATMOS 2010. LNCS, vol. 6448, pp. 105–115. Springer, Heidelberg (2011)

   Chapter  Google Scholar 

2. Baz, A., Shang, D., Xia, F., Yakovlev, A.: Self-Timed SRAM for Energy Harvesting Systems. Journal of Low Power Electronics 7(2), 274–284 (2011)

   Article  Google Scholar 

3. Gupta, S.K., Raychowdhury, A., Roy, K.: Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device–Circuit–Architecture Codesign Perspective. Proceedings of the IEEE 98(2), 160–190 (2010)

   Article  Google Scholar 

4. Qazi, M., Stawiasz, K., Chang, L., Chandrakasan, A.P.: A 512kb 8T SRAM Macro Operating Down to 0.57V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45nm SOI CMOS. IEEE Journal of Solid-State Circuits 46(1), 85–96 (2011)

   Article  Google Scholar 

5. Kulkarni, J.P., Roy, K.: Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (not published yet)

   Google Scholar 

6. Sit, Wing-Yun, V., Choy, C.-S., Chan, C.-F.: A Four-Phase Handshaking Asynchronous Static RAM Design for Self-Timed Systems. IEEE Journal of Solid-State Circuits 34(1), 90–96 (1999)

   Article  Google Scholar 

7. Dama, J., Lines, A.: GHz Asynchronous SRAM in 65nm. In: Proceedings of Asynchronous Circuits and Systems. In: 15th IEEE Symposium on ASYNC 2009, May 17-20, pp. 85–94 (2009)

   Google Scholar 

8. Chang, M.-F., Yang, S.-M., Chen, K.-T.: Wide Vdd Embedded Asynchronous SRAM With Dual-Mode Self-Timed Technique for Dynamic Voltage Systems. IEEE Transactions on Circuits and Systems I: Regular Papers 56(8), 1657–1667 (2009)

   Article  Google Scholar 

9. Noguchi, H., Okumura, S., Iguchi, Y., Fujiwara, H., Morita, Y., Nii, K., Kawaguchi, H., Yoshimoto, M.: Which is the Best Dual-Port SRAM in 45-nm Process Technology? — 8T, 10T single end, and 10T differential —. In: IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, 2008. ICICDT, June 2-4, pp. 55–58 (2008)

   Google Scholar 

10. Martin, A.J.: The Limitations to Delay-Insensitivity in Asynchronous Circuits. In: Dallyed, W.J. (ed.) Advanced Research in VLSI, pp. 263–278. MIT Press, Cambridge (1990)

    Google Scholar 

11. Amrutur, B.S., Horowitz, A.: A Replica technique for wordline and sense control in low power SRAM’s. IEEE Journal of Solid-State Circuits 33(8), 1208–1219 (1998)

    Article  Google Scholar 

12. Sparsø, J., Furber, S.: Principles of Asynchronus Circuit Design: A System Perspective. Kluwer Academic Publishers, Boston (2001)

    Book  Google Scholar 

13. Chen, Q., Mahmoodi, H., Bhunia, S., Roy, K.: Modeling and Testing of SRAM for New Failure Mechanisms due to Process Variations in nanoscale CMOS. In: Proceedings of the 23rd IEEE VLSI Test Symposium 9VTS 2005 (2005)

    Google Scholar 

14. Dilillo, L., A1-Hashimi, B.M., Rosinger, P., Girard, P.: Leakage Read Fault in Nanoscale SRAM:Analysis, test and Diagnosis. In: Proceedings of the International Design and Test Workshop, Duday, November 19-20 (2006)

    Google Scholar 

15. Shang, D., Yakovlev, A., Burns, F., Xia, F., Bystrov, A.: Low Cost Online Testing of Asynchronous Handshakes. In: Proceeding of European Testing Symposium (ETS), May 21-25 (2006)

    Google Scholar 

16. Cortadella, J., Kishinevsky, M., Kondratyev, A., Lavagno, L., Yakovlev, A.: Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IEICE Transactions on Information and Systems E80-D(3), 315–325 (1997)

    Google Scholar 

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