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Ki-Whan Song
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2020 – today
- 2022
- [c11]Jongmin Kim, Earl Kim, Jeongin Choe, Ki-Whan Song, Eun-Kyoung Kim, Jai Hyuk Song:
Machine Learning for Product Engineering in NAND Flash Memory. ICEIC 2022: 1-2 - [c10]Juwon Lee, Junho Seo, Jeonghun Nam, YongLae Kim, Ki-Whan Song, Jai Hyuk Song, Woo Young Choi:
Electric Field Impact on Lateral Charge Diffusivity in Charge Trapping 3D NAND Flash Memory. IRPS 2022: 29-1 - [c9]Bu-Il Nam, Young-Ha Choi, Sungki Hong, Ki-Young Dong, Wontaeck Jung, Sang-Won Park, Soon-Yong Lee, Dooyeun Jung, Byoung-Hee Kim, Eun-Kyoung Kim, Ki-Whan Song, Jai Hyuk Song, Woo Young Choi:
Novel Electrical Detection Method for Random Defects on Peripheral Circuits in NAND Flash Memory. IRPS 2022: 40-1 - 2020
- [c8]Doo-Hyun Kim, Hyunggon Kim, Sung-Won Yun, Youngsun Song, Jisu Kim, Sung-Min Joe, Kyung-Hwa Kang, Joonsuc Jang, Hyun-Jun Yoon, Kangbin Lee, Minseok Kim, Joonsoo Kwon, Jonghoo Jo, Sehwan Park, Jiyoon Park, Jisoo Cho, Sohyun Park, Garam Kim, Jinbae Bang, Heejin Kim, Jongeun Park, Deokwoo Lee, Seonyong Lee, Hwajun Jang, Hanjun Lee, Donghyun Shin, Jungmin Park, Jungkwan Kim, Jongmin Kim, Kichang Jang, II Han Park, Seung Hyun Moon, Myung-Hoon Choi, Pansuk Kwak, Joo-Yong Park, Youngdon Choi, Sanglok Kim, Seungjae Lee
, Dongku Kang, Jeong-Don Lim, Dae-Seok Byeon, Ki-Whan Song, Jung-Hwan Choi, Sangjoon Hwang, Jaeheon Jeong:
13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate. ISSCC 2020: 218-220
2010 – 2019
- 2019
- [c7]Dongku Kang, Minsu Kim, Suchang Jeon, Wontaeck Jung, Jooyong Park, Gyo Soo Choo, Dong-Kyo Shim, Anil Kavala, Seungbum Kim, Kyung-Min Kang, Jiyoung Lee, Kuihan Ko, Hyun Wook Park, ByungJun Min, Changyeon Yu, Sewon Yun, Nahyun Kim, Yeonwook Jung, Sungwhan Seo, Sunghoon Kim
A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface. ISSCC 2019: 216-218 - 2018
- [c6]Wooseong Cheong, Chanho Yoon, Seonghoon Woo, Kyuwook Han, Daehyun Kim, Chulseung Lee, Youra Choi, Shine Kim, Dongku Kang, Geunyeong Yu, Jaehong Kim, Jaechun Park, Ki-Whan Song, Ki-Tae Park, Sangyeun Cho, Hwaseok Oh, Daniel D. G. Lee, Jin-Hyeok Choi, Jaeheon Jeong:
A flash memory controller for 15μs ultra-low-latency SSD using high-speed 3D NAND flash with 3μs read time. ISSCC 2018: 338-340 - [c5]Seungjae Lee
A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput. ISSCC 2018: 340-342 - 2016
- [j6]Jinyoung Kim, Sang-Hoon Park, Hyeokjun Seo, Ki-Whan Song, Sungroh Yoon, Eui-Young Chung:
NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 764-768 (2016) - 2013
- [j5]Yong-Sung Cho, Il-Han Park, Sangyong Yoon, Nam-Hee Lee, Sang-Hyun Joo, Ki-Whan Song, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Young-Hyun Jun:
Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH. IEEE J. Solid State Circuits 48(4): 948-959 (2013) - 2012
- [c4]Daeyeal Lee, Ik Joon Chang, Sangyong Yoon, Joonsuc Jang, Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, ByungJun Min, Sung-Won Yun, Ji-Sang Lee, Il-Han Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yong-Sung Cho, Kyung-Min Kang, Sang-Hyun Joo, Jin-Young Chun, Jung-No Im, Seunghyuk Kwon, Seokjun Ham, Ansoo Park, Jae-Duk Yu, Nam-Hee Lee, Tae-Sung Lee, Moosung Kim, Hoosung Kim, Ki-Whan Song, Byung-Gil Jeon, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Youngho Lim, Young-Hyun Jun:
A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology. ISSCC 2012: 430-432 - [c3]Yong-Sung Cho, Il-Han Park, Sangyong Yoon, Nam-Hee Lee, Sang-Hyun Joo, Ki-Whan Song, Kihwan Choi, Jin-Man Han, Kyehyun Kyung, Young-Hyun Jun:
Adaptive multi-pulse program scheme based on tunneling speed classification for next generation multi-bit/cell NAND FLASH. VLSIC 2012: 136-137 - 2011
- [j4]Myounggon Kang, Ki-Whan Song, Byung-Gook Park, Hyungcheol Shin:
The novel SCR-based ESD protection with low triggering and high holding voltages. Microelectron. J. 42(6): 837-839 (2011) - [c2]Hoeju Chung, Byung-Hoon Jeong, ByungJun Min, Youngdon Choi, Beak-Hyung Cho, Junho Shin, Jinyoung Kim, Jung Sunwoo, Joon-min Park, Qi Wang, Yong-jun Lee, Sooho Cha, Dukmin Kwon, Sang-Tae Kim, Sunghoon Kim
A 58nm 1.8V 1Gb PRAM with 6.4MB/s program BW. ISSCC 2011: 500-502 - 2010
- [j3]Ki-Whan Song, Jinyoung Kim, Jae-Man Yoon, Sua Kim, Huijung Kim, Hyun-Woo Chung, Hyungi Kim, Kanguk Kim, Hwan-Wook Park, Hyun Chul Kang, Nam-Kyun Tak, Dukha Park, Woo-Seop Kim, Yeong-Taek Lee, Yong Chul Oh, Gyo-Young Jin, Jei-Hwan Yoo, Donggun Park, Kyungseok Oh, Changhyun Kim, Young-Hyun Jun:
A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency. IEEE J. Solid State Circuits 45(4): 880-888 (2010)
2000 – 2009
- 2006
- [j2]Churoo Park, Hoeju Chung, Yun-Sang Lee, Jaekwan Kim, JaeJun Lee, Moo Sung Chae, Dae-Hee Jung, Sung-Ho Choi, Seung-young Seo, Taek-Seon Park, Jun-Ho Shin, Jin-Hyung Cho, Seunghoon Lee, Ki-Whan Song, Kyu-Hyoun Kim
A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques. IEEE J. Solid State Circuits 41(4): 831-838 (2006) - 2003
- [c1]Ki-Whan Song, Sang-Hoon Lee, Dae Hwan Kim, Kyung Rok Kim, Jaewoo Kyung, Gwanghyeon Baek, Chun-An Lee, Jong Duk Lee, Byung-Gook Park:
Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic. ISMVL 2003: 267-272 - 2001
- [j1]Kyehyun Kyung, Hi-Choon Lee, Ki-Whan Song, Ho-Sung Song, Keewook Jung, Joon-Seo Moon, Byoung-Sul Kim, Sung-Burn Cho, Changhyun Kim, Soo-In Cho:
A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity. IEEE J. Solid State Circuits 36(5): 735-743 (2001)
Coauthor Index
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