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Sylvain Engels
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2020 – today
- 2024
- [c19]Xavier Lesage, Cristiano Merio, Fernando Welzel, Luca Sauer de Araujo, Sylvain Engels, Laurent Fesquet:
Data-driven Processing Element for Sparse Convolutional Neural Networks. NewCAS 2024: 143-147 - 2023
- [c18]Cristiano Merio, Xavier Lesage, Ali Naimi, Sylvain Engels, Katell Morin-Allory, Laurent Fesquet:
Method for Data-Driven Pruning in Micropipeline Circuits. VLSI-SoC 2023: 1-6 - 2022
- [c17]Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet:
A Novel Event-Based Method for ASK Demodulation. LASCAS 2022: 1-4 - 2021
- [c16]Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet:
Comparison between an ASK Event-Based Demodulation and a Digital IQ Demodulation. EBCCSP 2021: 1-4
2010 – 2019
- 2019
- [c15]Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet:
An Event-Based Strategy for ASK demodulation. EBCCSP 2019: 1-5 - [c14]Laurent Fesquet, Yoan Decoudu, Alexis Rodrigo Iga Jadue, Thiago Ferreira de Paiva Leite, Otto Aureliano Rolloff, M. Diallo, Rodrigo Possamai Bastos, Katell Morin-Allory, Sylvain Engels:
A Distributed Body-Biasing Strategy for Asynchronous Circuits. VLSI-SoC 2019: 27-32 - [c13]Alexis Rodrigo Iga Jadue, Sylvain Engels, Laurent Fesquet:
A Digital Event-Based Strategy for ASK demodulation. VLSI-SoC 2019: 244-245 - 2018
- [j6]Marc Renaudin, Aymane Bouzafour, Sylvain Engels, Robin Wilson:
A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI. J. Low Power Electron. 14(3): 404-413 (2018) - [c12]Sophie Germain, Sylvain Engels, Laurent Fesquet:
A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits. ASYNC 2018: 28-29 - 2017
- [c11]Sophie Germain, Sylvain Engels, Laurent Fesquet:
Event-based design strategy for circuit electromagnetic compatibility. EBCCSP 2017: 1-7 - 2014
- [j5]Ivan Miro Panades, Edith Beigné
, Yvain Thonnart
A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC. IEEE J. Solid State Circuits 49(7): 1475-1486 (2014) - [c10]Marc Renaudin, Aurélien Buhrig, Charles Guillemet, Robin Wilson, Sylvain Engels:
Clockless Design Performance Monitoring for Nanometer Technologies. ASYNC 2014: 108-109 - 2013
- [c9]Edith Beigné, Alexandre Valentian, Bastien Giraud, Olivier Thomas, Thomas Benoist, Yvain Thonnart, Serge Bernard, Guillaume Moritz, Olivier Billoint, Y. Maneglia, Philippe Flatresse, Jean-Philippe Noel, Fady Abouzeid
Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. DATE 2013: 613-618 - [c8]Edith Beigné
A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC. ESSCIRC 2013: 57-60 - [c7]Philippe Flatresse, Bastien Giraud, Jean-Philippe Noel, Bertrand Pelloux-Prayer, Fabien Giner, Deepak-Kumar Arora, Franck Arnaud, Nicolas Planes, Julien Le Coz, Olivier Thomas, Sylvain Engels, Giorgio Cesana, Robin Wilson, Pascal Urard:
Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology. ISSCC 2013: 424-425 - 2011
- [c6]N. Ruiz Amador, Vincent Huard, E. Pion, Florian Cacho, Damien Croain, V. Robert, Sylvain Engels, Philippe Flatresse, Lorena Anghel
Bottom-up digital system-level reliability modeling. CICC 2011: 1-4 - [c5]Julien Le Coz, Philippe Flatresse, Sylvain Engels, Alexandre Valentian, Marc Belleville, Christine Raynaud, Damien Croain, Pascal Urard:
Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec. ISSCC 2011: 336-337 - 2010
- [j4]Nabila Moubdi, Philippe Maurine, Robin Wilson, Sylvain Engels, Nadine Azémard, Vincent Dumettier, Pierre Busson:
On-Chip Process Variability Monitoring Flow. J. Low Power Electron. 6(4): 601-606 (2010)
2000 – 2009
- 2009
- [j3]V. Migairou, Robin Wilson, Sylvain Engels, Zeqin Wu, Nadine Azémard, Philippe Maurine:
Timing margin evaluation with a simple statistical timing analysis flow. J. Embed. Comput. 3(3): 221-229 (2009) - [c4]Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azémard, Vincent Dumettier, Abhishek Bansal, Sebastien Barasinski, Alain Tournier, Guy Durieu, David Meyer, Pierre Busson, Sarah Verhaeren, Sylvain Engels:
Product On-Chip Process Compensation for Low Power and Yield Enhancement. PATMOS 2009: 247-255 - 2007
- [c3]V. Migairou, Robin Wilson, Sylvain Engels, Zeqin Wu, Nadine Azémard, Philippe Maurine:
A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. PATMOS 2007: 138-147 - 2006
- [j2]Sylvain Engels, Robin Wilson, Nadine Azémard, Philippe Maurine:
A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects. Integr. 39(4): 433-456 (2006) - [j1]B. Lasbouygues, Sylvain Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Logical effort model extension to propagation delay representation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1677-1684 (2006) - [c2]V. Migairou, Robin Wilson, Sylvain Engels, Nadine Azémard, Philippe Maurine:
Statistical Characterization of Library Timing Performance. PATMOS 2006: 468-476 - 2003
- [c1]B. Lasbouygues, Joel Schindler, Sylvain Engels, Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Continuous representation of the performance of a CMOS library. ESSCIRC 2003: 595-598
Coauthor Index
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