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Yaojun Zhang
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2020 – today
- 2024
- [j13]Shanshan Zheng, Guofeng Chen, Yaojun Zhang:
Maintainability analysis and comprehensive tradeoff of naval ships equipment based on PROMETHEE method. J. Control. Decis. 11(3): 375-384 (2024) - [i2]Yaojun Zhang, Lanpeng Ji, Georgios Aivaliotis, Charles C. Taylor:
Bayesian CART models for aggregate claim modeling. CoRR abs/2409.01908 (2024) - 2023
- [j12]Anjunyi Fan, Yihan Fu, Yaoyu Tao, Zhonghua Jin, Haiyue Han, Huiyu Liu, Yaojun Zhang, Bonan Yan
, Yuchao Yang
Hadamard product-based in-memory computing design for floating point neural network training. Neuromorph. Comput. Eng. 3(1): 14009 (2023) - [j11]Xiaoxi Wang
Exploring the Relationships between Land Surface Temperature and Its Influencing Factors Using Multisource Spatial Big Data: A Case Study in Beijing, China. Remote. Sens. 15(7): 1783 (2023) - [c29]Anjunyi Fan, Bo Hu, Zhonghua Jin, Haiyue Han, Yaojun Zhang, Yue Yang, Yuchao Yang, Bonan Yan, Ru Huang:
Live Demonstration: SRAM Compute-In-Memory Based Visual & Aural Recognition System. AICAS 2023: 1-2 - [c28]Yanjun Li
SRAM-Based Processing-In-Memory Design with Kullback-Leibler Divergence-Based Dynamic Precision Quantization. ACM Great Lakes Symposium on VLSI 2023: 189-192 - [i1]Yaojun Zhang, Lanpeng Ji, Georgios Aivaliotis, Charles Taylor:
Bayesian CART models for insurance claims frequency. CoRR abs/2303.01923 (2023) - 2022
- [c27]Yaojun Zhang, Gilbert M. Tumibay:
Stock Market Prediction Model Based on LSTM Deep Learning: The Case of Top Corporate Company in China. AIAM 2022: 451-455 - [c26]Kangyi Qiu, Yaojun Zhang, Bonan Yan, Ru Huang:
Heterogeneous Memory Architecture Accommodating Processing-in-Memory on SoC for AIoT Applications. ASP-DAC 2022: 383-388 - [c25]Bonan Yan, Jeng-Long Hsu, Pang-Cheng Yu, Chia-Chi Lee, Yaojun Zhang, Wenshuo Yue, Guoqiang Mei, Yuchao Yang, Yue Yang, Hai Li, Yiran Chen, Ru Huang:
A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications. ISSCC 2022: 188-190
2010 – 2019
- 2018
- [c24]Bonan Yan, Fan Chen, Yaojun Zhang, Chang Song, Hai Li, Yiran Chen:
Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices. DATE 2018: 109-112 - 2017
- [j10]Enes Eken, Ismail Bayram, Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai (Helen) Li
Giant Spin-Hall assisted STT-RAM and logic design. Integr. 58: 253-261 (2017) - [j9]Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai Li
An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory. IEEE Trans. Computers 66(9): 1478-1490 (2017) - [j8]Yaojun Zhang
Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1181-1192 (2017) - 2016
- [j7]Jianlei Yang
Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3): 380-393 (2016) - [c23]Xian Zhang, Guangyu Sun, Yaojun Zhang, Yiran Chen, Hai Li, Wujie Wen, Jia Di:
A novel PUF based on cell error rate distribution of STT-RAM. ASP-DAC 2016: 342-347 - [c22]Enes Eken, Ismail Bayram, Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai (Helen) Li, Yiran Chen:
Spin-Hall Assisted STT-RAM Design and Discussion. SLIP 2016: 7:1-7:4 - 2015
- [j6]Yaojun Zhang, Yong Li, Zhenyu Sun, Hai Li
Read Performance: The Newest Barrier in Scaled STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1170-1174 (2015) - [c21]Bonan Yan, Yaojun Zhang, Enes Eken, Wujie Wen, Weisheng Zhao, Yiran Chen:
Recent progresses of STT memory design and applications. ASICON 2015: 1-4 - [c20]Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai Li, Yiran Chen:
Giant spin hall effect (GSHE) logic design for low power application. DATE 2015: 1000-1005 - [c19]Bonan Yan, Zheng Li, Yaojun Zhang, Jianlei Yang, Hai Li
A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback. ACM Great Lakes Symposium on VLSI 2015: 69-74 - 2014
- [j5]Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang
PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(11): 1644-1656 (2014) - [c18]Xiaoxiao Liu
STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures. ASP-DAC 2014: 355-360 - [c17]Wujie Wen, Yaojun Zhang, Mengjie Mao, Yiran Chen:
State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System. DAC 2014: 35:1-35:6 - [c16]Enes Eken, Yaojun Zhang, Wujie Wen, Rajiv V. Joshi, Hai Li
A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability. DAC 2014: 63:1-63:6 - [c15]Mengjie Mao, Wujie Wen, Yaojun Zhang, Yiran Chen, Hai (Helen) Li
Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory. DAC 2014: 196:1-196:6 - 2013
- [j4]Yiran Chen, Weng-Fai Wong
On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations. ACM J. Emerg. Technol. Comput. Syst. 9(2): 16:1-16:22 (2013) - [j3]Yong Li, Yaojun Zhang, Hai Li, Yiran Chen, Alex K. Jones
C1C: A configurable, compiler-guided STT-RAM L1 cache. ACM Trans. Archit. Code Optim. 10(4): 52:1-52:22 (2013) - [c14]Wujie Wen, Yaojun Zhang, Lu Zhang, Yiran Chen:
Loadsa: A yield-driven top-down design method for STT-RAM array. ASP-DAC 2013: 291-296 - [c13]Jie Guo, Wujie Wen, Yaojun Zhang, Sicheng Li, Hai Li, Yiran Chen:
DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems. DATE 2013: 380-385 - [c12]Yaojun Zhang, Ismail Bayram, Yu Wang
ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications. ICCAD 2013: 9-16 - [c11]Bin Li, Baolei Li, Yang Mo, Yaojun Zhang:
Pseudo-Three-Dimensional Navigation in Helical Scan Security Inspection. ICIG 2013: 838-841 - [c10]Yaojun Zhang, Lu Zhang, Yiran Chen:
MLC STT-RAM design considering probabilistic and asymmetric MTJ switching. ISCAS 2013: 113-116 - 2012
- [j2]Yong Li, Yaojun Zhang, Yiran Chen, Alex K. Jones
Combating Write Penalties Using Software Dispatch for On-Chip MRAM Integration. IEEE Embed. Syst. Lett. 4(4): 82-85 (2012) - [j1]Zhenyu Sun, Xiang Chen, Yaojun Zhang, Hai Li, Yiran Chen:
Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder. ACM J. Emerg. Technol. Comput. Syst. 8(2): 13:1-13:16 (2012) - [c9]Yiran Chen, Yaojun Zhang, Peiyuan Wang:
Probabilistic design in spintronic memory and logic circuit. ASP-DAC 2012: 323-328 - [c8]Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang
PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method. DAC 2012: 1191-1196 - [c7]Yaojun Zhang, Xiaobin Wang, Yong Li, Alex K. Jones, Yiran Chen:
Asymmetry of MTJ switching and its implication to STT-RAM designs. DATE 2012: 1313-1318 - [c6]Yaojun Zhang, Lu Zhang, Wujie Wen, Guangyu Sun, Yiran Chen:
Multi-level cell STT-RAM: Is it realistic or just a dream? ICCAD 2012: 526-532 - [c5]Guangyu Sun, Yaojun Zhang, Yu Wang, Yiran Chen:
Improving energy efficiency of write-asymmetric memories by log style write. ISLPED 2012: 173-178 - [c4]Zhongyuan Chen, Yuru Zhang, Dangxiao Wang
iFeel6-BH1500: A large-scale 6-DOF haptic device. VECIMS 2012: 121-125 - 2011
- [c3]Yaojun Zhang, Xiaobin Wang, Yiran Chen:
STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view. ICCAD 2011: 471-477 - 2010
- [c2]Hao Hu, Yuru Zhang, Xiaowei Dai, Yaojun Zhang:
The analysis of resolution for cable-driven haptic device. ROBIO 2010: 715-719
2000 – 2009
- 2009
- [c1]Yaojun Zhang, Yuru Zhang, Xiaowei Dai, Yi Yang:
Workspace analysis of a novel 6-dof cable-driven parallel robot. ROBIO 2009: 2403-2408
Coauthor Index
aka: Hai (Helen) Li
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