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Mustafa Badaroglu
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2020 – today
- 2022
- [c22]Houman Zahedmanesh, Ivan Ciofi, Odysseas Zografos, Kristof Croes, Mustafa Badaroglu:
System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents. IRPS 2022: 1-7 - [e1]Mustafa Badaroglu, Shantanu Dutt:
Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, SLIP 2022, San Diego, California, 3 November 2022. ACM 2022, ISBN 978-1-4503-9536-6 [contents] - 2021
- [c21]Houman Zahedmanesh, Ivan Ciofi, Odysseas Zografos, Mustafa Badaroglu, Kristof Croes:
A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network. SLIP 2021: 1-7 - 2020
- [c20]Mustafa Badaroglu:
Outlook of device and assembly technologies enabling high-performance mobile computing: IRDS view (invited). SLIP 2020: 1
2010 – 2019
- 2018
- [j17]Farshad Firouzi, Amir M. Rahmani
, Kunal Mankodiya
Internet-of-Things and big data for smarter healthcare: From device to architecture, applications and analytics. Future Gener. Comput. Syst. 78: 583-586 (2018) - [j16]Bahar J. Farahani
Towards fog-driven IoT eHealth: Promises and challenges of IoT in medicine and healthcare. Future Gener. Comput. Syst. 78: 659-676 (2018) - [j15]Mustafa Badaroglu:
Interconnect-Aware Technology and Design Co-Optimization for the 5-nm Technology and Beyond. J. Low Power Electron. 14(2): 186-194 (2018) - 2017
- [j14]Erik P. DeBenedictis, Mustafa Badaroglu, An Chen, Thomas M. Conte
Sustaining Moore's Law with 3D Chips. Computer 50(8): 69-73 (2017) - [c19]Jeffrey A. Smith, Kai Ni, Ram Krishna Ghosh, Jeff Xu, Mustafa Badaroglu, P. R. Chidi Chidambaram, Suman Datta
Investigation of electrically gate-all-around hexagonal nanowire FET (HexFET) architecture for 5 nm node logic and SRAM applications. ESSDERC 2017: 188-191 - [c18]Mustafa Badaroglu, Jeff Xu, John Zhu, Da Yang, Jerry Bao, Seung Chul Song, Peijie Feng, Romain Ritzenthaler, Hans Mertens, Geert Eneman, Naoto Horiguchi, Jeffrey Smith, Suman Datta
PPAC scaling enablement for 5nm mobile SoC technology. ESSDERC 2017: 240-243 - 2016
- [c17]Mustafa Badaroglu, Jeff Xu:
Interconnect-aware device targeting from PPA perspective. ICCAD 2016: 26 - [c16]Seung Chul Song, J. Xu, D. Yang, K. Rim, P. Feng, Jerry Bao, J. Zhu, Joseph Wang, G. Nallapati, Mustafa Badaroglu, Praneeth Narayanasetti, B. Bucki, Jeff Fischer, Geoffrey Yeap:
Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes. VLSI Circuits 2016: 1-2 - 2015
- [c15]Seung Chul Song, J. Xu, N. N. Mojumder, K. Rim, D. Yang, Jerry Bao, J. Zhu, Joseph Wang, Mustafa Badaroglu, V. Machkaoutsan, Praneeth Narayanasetti, B. Bucki, Jeff Fischer, Geoffrey Yeap:
Holistic technology optimization and key enablers for 7nm mobile SoC. VLSIC 2015: 198- - 2014
- [c14]Mustafa Badaroglu, Kwok Ng, Mehdi Salmani Jelodar, SungGeun Kim, Gerhard Klimeck
More Moore landscape for system readiness - ITRS2.0 requirements. ICCD 2014: 147-152 - 2013
- [c13]Arindam Mallik, Paul Zuber, Tsung-Te Liu, Bharani Chava
TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. DAC 2013: 24:1-24:6 - 2010
- [j13]Mustafa Badaroglu, Ugur Halici
A Cascadable Random Neural Network Chip with Reconfigurable Topology. Comput. J. 53(3): 289-303 (2010)
2000 – 2009
- 2008
- [c12]Mustafa Badaroglu, Guy Decabooter, Francois Laulanet, Olivier Charlier:
Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment. DATE 2008: 873-878 - 2007
- [j12]Julien Ryckaert, Marian Verhelst
A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication. IEEE J. Solid State Circuits 42(11): 2515-2527 (2007) - [c11]Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen
Scalable Gate-Level Models for Power and Timing Analysis. ISCAS 2007: 2938-2941 - [c10]Claude Desset, Mustafa Badaroglu, Julien Ryckaert, Bart van Poucke:
Optimized Signal Acquisition for Low-Complexity and Low-Power IR-UWB Transceivers. VTC Spring 2007: 3135-3139 - 2006
- [j11]Mustafa Badaroglu, Claude Desset, Julien Ryckaert, Vincent De Heyn, Geert Van der Plas
Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling. EURASIP J. Wirel. Commun. Netw. 2006 (2006) - [j10]Charlotte Soens, Geert Van der Plas
Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate. IEEE J. Solid State Circuits 41(9): 2040-2051 (2006) - [j9]Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1146-1154 (2006) - [j8]Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen
Evolution of substrate noise generation mechanisms with CMOS technology scaling. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(2): 296-305 (2006) - [j7]Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen
SWAN: high-level simulation methodology for digital substrate noise generation. IEEE Trans. Very Large Scale Integr. Syst. 14(1): 23-33 (2006) - [c9]Julien Ryckaert, Mustafa Badaroglu, Vincent De Heyn, Geert Van der Plas, Pierluigi Nuzzo, Andrea Baschirotto, Stefano D'Amico, Claude Desset, Hans Suys, Michael Libois, Bart van Poucke, Piet Wambacq, Bert Gyselinckx:
A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS. ISSCC 2006: 368-377 - 2005
- [j6]Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas
Digital ground bounce reduction by supply current shaping and clock frequency Modulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(1): 65-76 (2005) - [j5]Julien Ryckaert, Claude Desset, Andrew Fort, Mustafa Badaroglu, Vincent De Heyn, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Bart van Poucke, Bert Gyselinckx:
Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(12): 2515-2525 (2005) - 2004
- [j4]Mustafa Badaroglu, Geert Van der Plas
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. IEEE J. Solid State Circuits 39(7): 1119-1130 (2004) - [c8]Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas
Impact of technology scaling on substrate noise generation mechanisms [mixed signal ICs]. CICC 2004: 501-504 - [c7]Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen
High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. DAC 2004: 854-859 - [c6]Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas
Digital Ground Bounce Reduction by Phase Modulation of the Clock. DATE 2004: 88-93 - 2003
- [j3]Mustafa Badaroglu, Stéphane Donnay, Hugo J. De Man, Yann A. Zinzius, Georges G. E. Gielen
Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies. IEEE J. Solid State Circuits 38(7): 1250-1260 (2003) - [c5]Mustafa Badaroglu, Lakshmanan Balasubramanian, Kris Tiri, Vincent Gravot, Piet Wambacq, Geert Van der Plas
Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate. ESSCIRC 2003: 257-260 - 2002
- [j2]Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Georges G. E. Gielen
Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification. IEEE J. Solid State Circuits 37(8): 1065-1072 (2002) - [j1]Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, John Compiet, Stéphane Donnay, Georges G. E. Gielen
Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits. IEEE J. Solid State Circuits 37(11): 1383-1395 (2002) - [c4]Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen:
Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. DAC 2002: 399-404 - 2001
- [c3]Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen
High-level simulation of substrate noise generation from large digital circuits with multiple supplies. DATE 2001: 326-330 - 2000
- [c2]Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels
High-level simulation of substrate noise generation including power supply noise coupling. DAC 2000: 446-451
1990 – 1999
- 1999
- [c1]Stéphane Donnay, Marc van Heijningen, Mustafa Badaroglu, Wim Diels, Marc Engels
BANDIT: embedding analog-to-digital converters on digital telecom ASICs. ICECS 1999: 1377-1380
Coauthor Index
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