Substrate noise generated by the switching digital circuits degrades the performance of analog circuits embedded on the same substrate.

This paper presents a complete high-level methodology, which simulates a large digital standard cell-based design using a net- work of substrate macromodels, ...

This paper presents a complete high-level methodology, which simulates a large digital standard cell-based design using a network of substrate macromodels, with ...

SWAN shows good correlation to SPICE simulations with approximately 6.3% error in the RMS voltage but with a speedup of 213 times for an 8-bit multiplier [12] .

SWAN: high-level simulation methodology for digital substrate noise generation · Engineering, Computer Science. IEEE Transactions on Very Large Scale Integration ...

implemented in SWAN. The improved high-level sub- strate noise simulation methodology (SWAN) can simu- late the substrate noise voltage within %6.3 of a full.

In this paper, we present a macromodeling methodology to predict substrate noise generated by large digital sections. The macromodel is generated element by ...

We have presented a methodology named SWAN (Substrate. Waveform ANalysis) [6][7], which accurately simulates the actual waveform of the substrate noise ...

Abstract—A methodology is proposed to efficiently analyze substrate noise coupled to a sensitive block due to an aggressor digital block in large-scale ...

SWAN: high-level simulation methodology for digital substrate noise generation · Modeling digital substrate noise injection in mixed-signal IC's · Accurate ...