Outlook of device and assembly technologies enabling high-performance mobile computing: IRDS view (invited)
Article No.: 1, Pages 1 - 7
Abstract
We are living in a connected world with access to data in vast amounts. This connectivity is enhanced by more intelligent sensors and human-computer interfaces bringing people closer to computation in a more natural and accessible way. Instant data generation requires ultra-low-power devices with an "always-on" feature at the same time with high-performance devices that can generate the data instantly. Big data requires abundant computing, communication bandwidth, and memory resources to generate services and sensible information that people need. But transfer of data becomes a limitation for the scaling of systems where both on-chip and off-chip interconnects become quite scarce in meeting this demand. In this paper we will present about these challenges, how they impact the outlook of More Moore technologies and 3D architectures in this interconnect-scarce era.
References
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M. Badaroglu et al., "PPAC scaling enablement for 5nm mobile SoC technology," ESSDERC'2017, September 2017.
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C. Auth et al., "A 10nm high performance and low-power CMOS technology featuring 3rd-generation finFET transistors, self-aligned quad patterning, contact over active gate and Cobalt local interconnects," IEDM, December 2017.
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S.K. Moore, "A better way to measure progress in semiconductors," "The node is nonsense," IEEE Spectrum, August 2020.
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M. Badaroglu, "3D IC opportunities for high-performance computing", Semi 3D & Systems summit, January 2020.
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G. Yeap et al., "5nm CMOS production technology platform featuring full-fledged EUV, and high mobility channel FinFETs with densest 0.021 um2 SRAM cells for mobile SoC and high-performance computing applications," IEDM, December 2019.
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Published: 14 December 2020
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SLIP '20
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SLIP '20: System-Level Interconnect - Problems and Pathfinding Workshop
November 5, 2020
California, San Diego
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Overall Acceptance Rate 6 of 8 submissions, 75%
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