This paper proposes TEASE (Technology Exploration and Analysis for SoC-level Evaluation), a framework to systematically analyze and evaluate system design in finFET-based technology node. The proposed framework combines both lithography and electrical constraints of a particular technology node to optimize the standard cell library performance. Growing complexity of logic design at nodes below 20nm causes to adopt a design style that can embrace the simplicity required to enable manufacturing, along with a process technology that can be finely tuned to the desired performance constraints. Additionally, the introduction of finFET based devices poses a new challenge for the designers to come up with an efficient standard cell template. The proposed framework can be used to detect the technology constraints that act as the bottleneck for the enablement of design at these advanced nodes. Results presented in this paper show by optimizing these bottlenecks we can improve the performance of a standard cell library significantly. Furthermore, adapting to such an analysis framework at an early stage of technology development helps to take the design constraints into the decision loop for realization of technology research into real products.

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Cited By

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Xu XShah NEvans ASinha SCline BYeric GParameswaran S(2017)Standard cell library design and optimization methodology for ASAP7 PDKProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199838(999-1004)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199838
Xu XShah NEvans ASinha SCline BYeric G(2017)Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper)2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2017.8203890(999-1004)Online publication date: Nov-2017
https://doi.org/10.1109/ICCAD.2017.8203890
Wang WGupta P(2016)Efficient Layout Generation and Design Evaluation of Vertical Channel DevicesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.251367435:9(1449-1460)Online publication date: Sep-2016
https://doi.org/10.1109/TCAD.2015.2513674
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Index Terms

TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes
1. Hardware
  1. Emerging technologies

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DAC '13: Proceedings of the 50th Annual Design Automation Conference

May 2013

1285 pages

ISBN:9781450320719

DOI:10.1145/2463209

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Cited By

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Xu XShah NEvans ASinha SCline BYeric GParameswaran S(2017)Standard cell library design and optimization methodology for ASAP7 PDKProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199838(999-1004)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199838
Xu XShah NEvans ASinha SCline BYeric G(2017)Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper)2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2017.8203890(999-1004)Online publication date: Nov-2017
https://doi.org/10.1109/ICCAD.2017.8203890
Wang WGupta P(2016)Efficient Layout Generation and Design Evaluation of Vertical Channel DevicesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.251367435:9(1449-1460)Online publication date: Sep-2016
https://doi.org/10.1109/TCAD.2015.2513674
Ye WYu BPan DBan YLiebmann LJones ALi HCoskun AMargala M(2015)Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-LineProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742084(289-294)Online publication date: 20-May-2015
https://dl.acm.org/doi/10.1145/2742060.2742084
Zimpeck AMeinhardt CPosser GReis R(2015)Process variability in FinFET standard cells with different transistor sizing techniques2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)10.1109/ICECS.2015.7440264(121-124)Online publication date: Dec-2015
https://doi.org/10.1109/ICECS.2015.7440264
Hsu MKatta NLin HLin KTam KWang KChang Y(2014)Design and manufacturing process co-optimization in nano-technologyProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691480(574-581)Online publication date: 3-Nov-2014
https://dl.acm.org/doi/10.5555/2691365.2691480
Wang WGupta PChang Y(2014)Efficient layout generation and evaluation of vertical channel devicesProceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design10.5555/2691365.2691475(550-556)Online publication date: 3-Nov-2014
https://dl.acm.org/doi/10.5555/2691365.2691475
Hsu MKatta NLin HLin KTam KWang K(2014)Design and manufacturing process co-optimization in nano-technology (Designer Track Paper)2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2014.7001408(574-581)Online publication date: Nov-2014
https://doi.org/10.1109/ICCAD.2014.7001408
Wang WGupta P(2014)Efficient layout generation and evaluation of vertical channel devices2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2014.7001404(550-556)Online publication date: Nov-2014
https://doi.org/10.1109/ICCAD.2014.7001404

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