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Journal of Electronic Testing, Volume 34
Volume 34, Number 1, February 2018
- Vishwani D. Agrawal:
Editorial. 1 - New Editor - 2018. 3
- Test Technology Newsletter. 5-6
- Mostafa E. Salehi, Ali Azarpeyvand
, Armin Hajaboutalebi Aboutalebi:
Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints. 7-14 - Xiaozhi Du
FFI4SoC: a Fine-Grained Fault Injection Framework for Assessing Reliability against Soft Error in SoC. 15-25 - Yang Yu
NBTI and Power Reduction Using a Workload-Aware Supply Voltage Assignment Approach. 27-41 - Davide Appello, Paolo Bernardi
Adaptive Management Techniques for Optimized Burn-in of Safety-Critical SoC. 43-52 - Toral Shah
Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design. 53-65 - Michael A. Skitsas, Chrysostomos A. Nicopoulos
Exploring System Availability During Software-Based Self-Testing of Multi-core CPUs. 67-81 - Vasudevan Madampu Suryasarman, Santosh Biswas, Aryabartta Sahu:
Automation of Test Program Synthesis for Processor Post-silicon Validation. 83-103
Volume 34, Number 2, April 2018
- Vishwani D. Agrawal:
Editorial. 105 - Test Technology Newsletter. 107-108
- Mengbo Sun, Hongjun Lv, Yongqiang Zhang, Guangjun Xie:
The Fundamental Primitives with Fault-Tolerance in Quantum-Dot Cellular Automata. 109-122 - Freddy Forero
Detectability Challenges of Bridge Defects in FinFET Based Logic Cells. 123-134 - Pralhadrao V. Shantagiri
Handling Unknown with Blend of Scan and Scan Compression. 135-146 - Naoki Terao
Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment. 147-161 - Eman El Mandouh, Amr G. Wassal:
Application of Machine Learning Techniques in Post-Silicon Debugging and Bug Localization. 163-181 - Rana Elnaggar, Krishnendu Chakrabarty
Machine Learning for Hardware Security: Opportunities and Risks. 183-201 - Yong Gao, En Li, Gaofeng Guo:
Measurement of Nonlinear Dielectric Behaviour of Semiconductor Material Under Microwave Field in Dual-Mode Rectangular Cavity. 203-207
Volume 34, Number 3, June 2018
- Vishwani D. Agrawal:
Editorial. 209 - Test Technology Newsletter. 211-212
- Ke Huang, Manuel J. Barragán:
Guest Editorial: Special Issue on Analog, Mixed-Signal, and RF Testing. 213-214 - Peter Sarson, Tomonori Yanagida, Shohei Shibuya, Kosuke Machida, Haruo Kobayashi:
A Distortion Shaping Technique to Equalize Intermodulation Distortion Performance of Interpolating Arbitrary Waveform Generators in Automated Test Equipment. 215-232 - Peter Sarson, Tomonori Yanagida, Kosuke Machida:
Measuring Group Delay of Frequency Downconverter Devices Using a Chirped RF Modulated Signal. 233-253 - Siyuan Yan, Xiao Li, Changhong Jiang, Hui Li, Lingmei Wang, Fu Li:
Digital Predistortion for Spectrum Compliance in the Internet of Things. 255-262 - Hani Malloug, Manuel J. Barragán
Practical Harmonic Cancellation Techniques for the On-Chip Implementation of Sinusoidal Signal Generators for Mixed-Signal BIST Applications. 263-279 - Stephane David-Grignot, Achraf Lamlih, Mohamed Moez Belhaj, Vincent Kerzerho, Florence Azaïs, Fabien Soulier
On-chip Generation of Sine-wave Summing Digital Signals: an Analytic Study Considering Implementation Constraints. 281-290 - Yassine Naija
Security Enhancements of a Mutual Authentication Protocol Used in a HF Full-Fledged RFID Tag. 291-304 - Yang Zhang
Golden-Free Processor Hardware Trojan Detection Using Bit Power Consistency Analysis. 305-312 - Congyin Shi, Sanghoon Lee
A Time-Domain Digital-Intensive Built-In Tester for Analog Circuits. 313-320 - Ahcène Bounceur
A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters. 321-335 - Parth Kansara, Sharanabasavaraja Bheema Reddy, Louay Abdallah, Ke Huang
Dynamic Analog/RF Alternate Test Strategies Based on On-chip Learning. 337-349 - Roya Dibaj
Gate Oxide Short Defect Model in FinFETs. 351-362 - B. Mert Gönültas, Janset Savas, Ramin Khayatzadeh, Sacid Aygün, Fehmi Çivitci, Y. Daghan Gökdel, M. Berke Yelten, Onur Ferhanoglu:
Reliability Testing of 3D-Printed Electromechanical Scanning Devices. 363-370
Volume 34, Number 4, August 2018
- Vishwani D. Agrawal:
Editorial. 371-372 - Test Technology Newsletter. 373-374
- Lorena Anghel
Test and Reliability in Approximate Computing. 375-387 - R. Jothin
High Performance Static Segment On-Chip Memory for Image Processing Applications. 389-404 - Aydin Dirican
Leakage-Aware Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators. 405-415 - Felipe G. A. e Silva, Jardel Silveira, Jarbas Silveira
An Extensible Code for Correcting Multiple Cell Upset in Memory Arrays. 417-433 - Shyue-Kung Lu
Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories. 435-446 - Ying Zhang, Li Ling, Jianhui Jiang, Jie Xiao:
Thermal-aware SoC Test Scheduling with Voltage/Frequency Scaling and Test Partition. 447-460 - M. A. Nourian, Mahdi Fazeli
Hardware Trojan Detection Using an Advised Genetic Algorithm Based Logic Testing. 461-470 - Riadul Islam
Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops. 471-485 - Marcos T. Leipnitz
Fault Tolerance Mechanisms for FPGA-Based Regular Expression Matching. 487-506
Volume 34, Number 5, October 2018
- Vishwani D. Agrawal:
Editorial. 507-508 - Test Technology Newsletter. 509-510
- Muhammad Osama
An Efficient SAT-Based Test Generation Algorithm with GPU Accelerator. 511-527 - Shigang Zhang, Long Wang, Ying Liu, Xiaofei Zhang
Real Time Fault Diagnosis with Tests of Uncertain Quality for Multimode Systems and its Application in a Satellite Power System. 529-545 - Vladimir Chepelev, Yury Parfenov, William Radasky, Boris Titov, Leonid Zdoukhov, Kejie Li, Yuhao Chen, Xu Kong, Yan-zhao Xie
Methodical Approach for Immunity Assessment of Electronic Devices Excited by High Power EMP. 547-557 - Shyue-Kung Lu
Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories. 559-570 - Naghmeh Karimi
Impact of Aging on the Reliability of Delay PUFs. 571-586 - Weize Yu
Exploiting Multi-Phase On-Chip Voltage Regulators as Strong PUF Primitives for Securing IoT. 587-598 - J. Qing, Y. Zeng, Xiaojin Li
Analytical Low Frequency NBTI Compact Modeling with H2 Locking and Electron Fast Capture and Emission. 599-605 - R. Jothin
High Performance Modified Static Segment Approximate Multiplier based on Significance Probability. 607-614
Volume 34, Number 6, December 2018
- Vishwani D. Agrawal:
Editorial. 615-617 - 2017 JETTA-TTTC Best Paper Award. 621-622
- Vaishali H. Dhare
Multiple Missing Cell Defect Modeling for QCA Devices. 623-641 - Xu Bai
Blind Calibration Method for Two-Channel Time-Interleaved Analog-to-Digital Converters Based on FFT. 643-650 - Abdus Sami Hassan, Tooba Arifeen
Generation Methodology for Good-Enough Approximate Modules of ATMR. 651-665 - Stelios N. Neophytou
Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering. 667-683 - Haiying Yuan
LFSR Reseeding-Oriented Low-Power Test-Compression Architecture for Scan Designs. 685-695 - Vijaypal Singh Rathor
New Lightweight Architectures for Secure FSM Design to Thwart Fault Injection and Trojan Attacks. 697-708 - Dragan Lambic
Security Analysis of the Efficient Chaos Pseudo-random Number Generator Applied to Video Encryption. 709-715 - Xiaozhi Du
A Fine-Grained Software-Implemented DMA Fault Tolerance for SoC Against Soft Error. 717-733 - Pablo Ilha Vaz
Design Flow Methodology for Radiation Hardened by Design CMOS Enclosed-Layout-Transistor-Based Standard-Cell Library. 735-747 - Nabil El Belghiti Alaoui, Alexandre Boyer, Patrick Tounsi, Arnaud Viard:
Upgrading In-Circuit Test of High Density PCBAs Using Electromagnetic Measurement and Principal Component Analysis. 749-762 - Wei Jiang
A Simplified Calibration Methodology for On-Chip Couplers. 763-768
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