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Design Flow Methodology for Radiation Hardened by Design CMOS Enclosed-Layout-Transistor-Based Standard-Cell Library

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Abstract

Ionizing radiation degrades the electrical characteristics of MOS devices, reducing their reliability, performance, and lifetime; therefore, hardening techniques are required for the proper functioning of those devices when exposed to harsh environments. Nonetheless, in the context of design flow automation, necessary to synthesize complex digital circuits, there is a lack of reliable foundry-provided Radiation Hardening by Design (RHBD) cell libraries. In this work, a complete RHBD flow methodology employing enclosed-layout transistors (ELTs) and guard rings, transparent to the designer, and fully compatible with commercial CAD tools and standard fabrication processes is presented. The proposed flow includes the automated calculation of the effective aspect ratio of the ELTs for annular and rectangular topologies, and a template proposal for digital cells, as well as series and parallel arrangements. Moreover, calculation of aspect ratio between pull-up and down networks and output buffers sizing using Logical Effort (LE) methodology, i.e., timing optimization accounting for typical commercial digital design constraints, is considered. Test structures, enclosing single n,pMOS devices, series and parallel arrangements, inverter cells, ring oscillators, and output buffers, were fabricated in two different technology nodes (600 nm and 180 nm). The experimental results were compared to SPICE simulations performed using the models here implemented. The results indicate that the flow methodology is feasible to implement and fully compatible with the CAD tools employed for circuit design. Besides, two case studies were first silicon-proven, presenting fully functional behavior under typical conditions.

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Acknowledgments

The authors would like to thank CNPq for financial support.

This study was financed in part by the Coordenação de Aperfeiçoamento de Pessoal de Nível Superior - Brasil (CAPES) - Finance Code 001.

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Authors and Affiliations

  1. Programa de Pós-Graduação em Microeletrônica (PGMICRO/UFRGS), Porto Alegre, Brazil

    Pablo Ilha Vaz, Thiago Hanna Both, Fábio Fedrizzi Vidor & Gilson Inácio Wirth

  2. Departamento de Engenharia Elétrica (DELET/UFRGS), Av. Osvaldo Aranha, 103, Porto Alegre, RS, 91501-970, Brazil

    Raphael Martins Brum

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  1. Pablo Ilha Vaz
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  2. Thiago Hanna Both
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Correspondence to Pablo Ilha Vaz.

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Responsible Editor: R. D. Blanton

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Vaz, P.I., Both, T.H., Vidor, F.F. et al. Design Flow Methodology for Radiation Hardened by Design CMOS Enclosed-Layout-Transistor-Based Standard-Cell Library. J Electron Test 34, 735–747 (2018). https://doi.org/10.1007/s10836-018-5760-7

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  • DOI: https://doi.org/10.1007/s10836-018-5760-7

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