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IEEE Computer Architecture Letters, Volume 18
Volume 18, Number 1, January - June 2019
- Jiho Kim
, Jehee Cha, Jason Jong Kyu Park
Improving GPU Multitasking Efficiency Using Dynamic Resource Sharing. 1-5 - Sheng Xu
PIMSim: A Flexible and Detailed Processing-in-Memory Simulator. 6-9 - Gil Shomron
Spatial Correlation and Value Prediction in Convolutional Neural Networks. 10-13 - Ujjwal Gupta
A Deep Q-Learning Approach for Dynamic Management of Heterogeneous Processors. 14-17 - Samuel Rogers
Scalable LLVM-Based Accelerator Modeling in gem5. 18-21 - Berkin Akin
A Case For Asymmetric Processing in Memory. 22-25 - Konstantinos Tovletoglou
Shimmer: Implementing a Heterogeneous-Reliability DRAM Framework on a Commodity Server. 26-29 - Chanchal Kumar
Hybrid Remote Access Protocol. 30-33 - Yicheng Wang
Detect DRAM Disturbance Error by Using Disturbance Bin Counters. 34-37 - Xinfeng Xie
NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs. 38-42 - Asif Ali Khan
RTSim: A Cycle-Accurate Simulator for Racetrack Memories. 43-46 - Yiming Gan
SVSoC: Speculative Vision Systems-on-a-Chip. 47-50 - Ting-Ru Lin
Design Space Exploration of Memory Controller Placement in Throughput Processors with Deep Learning. 51-54 - Yehia Arafa
PPT-GPU: Scalable GPU Performance Modeling. 55-58 - Bradley Denby
Orbital Edge Computing: Machine Inference in Space. 59-62 - He Liu
A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration. 63-66 - Tian Tan
Dark Wires and the Opportunities for Reconfigurable Logic. 67-70 - Ajeya Naithani
Precise Runahead Execution. 71-74 - Varun Agrawal
Massively Parallel Server Processors. 75-78 - Hossein Golestani
Performance Modeling and Bottleneck Analysis of EDGE Processors Using Dependence Graphs. 79-82 - Jingwen Leng
Asymmetric Resilience for Accelerator-Rich Systems. 83-86
Volume 18, Number 2, July - December 2019
- Elaheh Sadredini
A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing. 87-90 - Ahmad Yasin
Tuning Performance via Metrics with Expectations. 91-94 - Lu Wang
Modeling Emerging Memory-Divergent GPU Applications. 95-98 - Gil Shomron
SMT-SA: Simultaneous Multithreading in Systolic Arrays. 99-102 - Dimosthenis Masouros
Rusty: Runtime System Predictability Leveraging LSTM Neural Networks. 103-106 - Sunwoong Kim
HAD-TWL: Hot Address Detection-Based Wear Leveling for Phase-Change Memory Systems with Low Latency. 107-110 - Huiyang Zhou
Quantum Circuits for Dynamic Runtime Assertions in Quantum Computation. 111-114 - Jinli Rao
ARCE: Towards Code Pointer Integrity on Embedded Processors Using Architecture-Assisted Run-Time Metadata Management. 115-118 - Kshitij Bhardwaj
Determining Optimal Coherency Interface for Many-Accelerator SoCs Using Bayesian Optimization. 119-123 - Ali Ansari
Code Layout Optimization for Near-Ideal Instruction Cache. 124-127 - Kiran Ranganath
Speeding up Collective Communications Through Inter-GPU Re-Routing. 128-131 - Dylan C. Stow
Power Profiling of Modern Die-Stacked Memory. 132-135 - Seyed Morteza Nabavinejad
Coordinated DVFS and Precision Control for Deep Neural Networks. 136-140 - Seunghak Lee, Nam Sung Kim
Exploiting OS-Level Memory Offlining for DRAM Power Management. 141-144 - Theodoros Marinakis
Performance and Fairness Improvement on CMPs Considering Bandwidth and Cache Utilization. 145-148 - Adarsha Balaji
A Framework to Explore Workload-Specific Performance and Lifetime Trade-offs in Neuromorphic Computing. 149-152 - Hyeran Jeon
Locality-Aware GPU Register File. 153-156 - Chen Li
Priority-Based PCIe Scheduling for Multi-Tenant Multi-GPU Systems. 157-160 - Jian Weng
DAEGEN: A Modular Compiler for Exploring Decoupled Spatial Accelerators. 161-165 - Konstantinos Iliakis
LOOG: Improving GPU Efficiency With Light-Weight Out-Of-Order Execution. 166-169 - Reoma Matsuo
Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline. 170-173 - Vamsee Reddy Kommareddy
Are Crossbar Memories Secure? New Security Vulnerabilities in Crossbar Memories. 174-177 - Kristin Barber, Anys Bacha
Isolating Speculative Data to Prevent Transient Execution Attacks. 178-181
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