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Ramon Bertran Monfort
Person information
- affiliation: IBM Research, Yorktown Heights, NY, USA
- affiliation (former): Barcelona Supercomputing Center
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2020 – today
- 2024
- [c23]Karthik Swaminathan, Ramon Bertran, Alper Buyuktosunoglu, Pradip Bose:
FitBit: Ensuring Robust and Secure Execution Through Runtime-Generated Stressmarks. HOST 2024: 194-198 - 2023
- [j16]Cristobal Ortega
, Lluc Alvarez
Adaptive Power Shifting for Power-Constrained Heterogeneous Systems. IEEE Trans. Computers 72(3): 627-640 (2023) - [c22]Karthik Swaminathan, Ramon Bertran, Doug Balazich, Alper Buyuktosunoglu, Arvind Haran, Sean M. Carey, Karl Anderson, Hans M. Jacobson, Matthias Pflanz, Pradip Bose:
Characterization and Exploration of Latch Checkers for Efficient RAS Protection. DSN-S 2023: 63-69 - 2022
- [c21]Cédric Lichtenau, Alper Buyuktosunoglu, Ramon Bertran, Peter Figuli, Christian Jacobi, Nikolaos Papandreou, Haris Pozidis, Anthony Saporito, Andrew Sica, Elpida Tzortzatos:
AI accelerator on IBM telum processor: industrial product. ISCA 2022: 1012-1028 - 2021
- [j15]David Wolpert
Cores, Cache, Content, and Characterization: IBM's Second Generation 14-nm Product, z15. IEEE J. Solid State Circuits 56(1): 98-111 (2021) - [j14]Cristobal Ortega
Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption. IEEE Trans. Computers 70(1): 1-16 (2021) - [j13]Jingwen Leng
Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(1): 171-184 (2021) - [j12]Jingwen Leng
Erratum to "Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(6): 1272 (2021) - [c20]Karthik Swaminathan, Ramon Bertran, Hans M. Jacobson, Pradip Bose, Matthias Pflanz, Doug Balazich:
SERMiner : A Framework for Early-stage Reliability Estimation for IBM Processors. DSN (Supplements) 2021: 61-64 - [c19]Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam
Energy Efficiency Boost in the AI-Infused POWER10 Processor. ISCA 2021: 29-42 - [c18]Gokul Subramanian Ravi, Ramon Bertran, Pradip Bose, Mikko H. Lipasti:
MicroGrad: A Centralized Framework for Workload Cloning and Stress Testing. ISPASS 2021: 70-72 - [i2]José E. Moreira, Kit Barton, Steven Battle, Peter Bergner, Ramon Bertran, Puneeth Bhat, Pedro Caldeira, David Edelsohn, Gordon C. Fossum, Brad Frey, Nemanja Ivanovic, Chip Kerchner, Vincent Lim, Shakti Kapoor, Tulio Machado Filho, Silvia Melitta Mueller, Brett Olsson, Satish Sadasivam, Baptiste Saleil, Bill Schmidt, Rajalakshmi Srinivasaraghavan, Shricharan Srivatsan, Brian W. Thompto, Andreas Wagner, Nelson Wu:
A matrix math facility for Power ISA(TM) processors. CoRR abs/2104.03142 (2021) - 2020
- [j11]Tobias Webel, Preetham M. Lobo, Thomas Strach, Pradeep Bhadravati Parashurama, Srinivas Purushotham, Ramon Bertran, Alper Buyuktosunoglu:
Proactive power management in IBM z15. IBM J. Res. Dev. 64(5/6): 15:1-15:12 (2020) - [c17]Jingwen Leng, Alper Buyuktosunoglu, Ramon Bertran
Asymmetric Resilience: Exploiting Task-Level Idempotency for Transient Error Recovery in Accelerator-Based Systems. HPCA 2020: 44-57 - [c16]Christopher J. Berry, Brian Bell, Adam Jatkowski, Jesse Surprise, John Isakson, Ofer Geva, Brian Deskin, Mark Cichanowski, Dina Hamid, Chris Cavitt, Gregory Fredeman, Anthony Saporito, Ashutosh Mishra, Alper Buyuktosunoglu, Tobias Webel, Preetham Lobo, Pradeep Parashurama, Ramon Bertran
2.7 IBM z15: A 12-Core 5.2GHz Microprocessor. ISSCC 2020: 54-56 - [i1]Gokul Subramanian Ravi, Ramon Bertran, Pradip Bose, Mikko H. Lipasti:
MicroGrad: A Centralized Framework for Workload Cloning and Stress Testing. CoRR abs/2009.04622 (2020)
2010 – 2019
- 2019
- [j10]Jingwen Leng
Asymmetric Resilience for Accelerator-Rich Systems. IEEE Comput. Archit. Lett. 18(1): 83-86 (2019) - [j9]Christopher J. Berry
IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems. IEEE J. Solid State Circuits 54(1): 121-132 (2019) - [c15]Karthik Swaminathan, Ramon Bertran
Generation of Stressmarks for Early Stage Soft-Error Modeling. DSN (Supplements) 2019: 42-48 - 2018
- [j8]Eric J. Fluhr, Rahul M. Rao, Howard Smith, Alper Buyuktosunoglu, Ramon Bertran Monfort
IBM POWER9 circuit design and energy optimization for 14-nm technology. IBM J. Res. Dev. 62(4/5): 4:1-4:11 (2018) - [c14]Calvin Bulla, Lluc Alvarez
ChopStiX: Systematic Extraction of Code-Representative Microbenchmarks. IISWC 2018: 80-81 - [c13]Christos Vezyrtzis, Thomas Strach, Pierce I-Jen Chuang, Preetham Lobo, Richard F. Rizzolo, Tobias Webel, Pawel Owczarczyk, Alper Buyuktosunoglu, Ramon Bertran
Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor. ISSCC 2018: 300-302 - 2017
- [j7]Matthew M. Ziegler, Ramon Bertran Monfort
Machine learning techniques for taming the complexity of modern hardware design. IBM J. Res. Dev. 61(4-5): 13:1-13:14 (2017) - [c12]Karthik Swaminathan, Nandhini Chandramoorthy, Chen-Yong Cher, Ramon Bertran
BRAVO: Balanced Reliability-Aware Voltage Optimization. HPCA 2017: 97-108 - [c11]Ramon Bertran
Very Low Voltage (VLV) Design. ICCD 2017: 601-604 - [c10]Cristobal Ortega
libPRISM: an intelligent adaptation of prefetch and SMT levels. ICS 2017: 28:1-28:10 - [c9]Pierce I-Jen Chuang, Christos Vezyrtzis, Divya Pathak, Richard F. Rizzolo, Tobias Webel, Thomas Strach, Otto A. Torreiter, Preetham Lobo, Alper Buyuktosunoglu, Ramon Bertran
26.2 Power supply noise in a 22nm z13™ microprocessor. ISSCC 2017: 438-439 - 2015
- [j6]Tobias Webel, Preetham M. Lobo, Ramon Bertran
Robust power management in the IBM z13. IBM J. Res. Dev. 59(4/5) (2015) - [c8]Jingwen Leng, Alper Buyuktosunoglu, Ramon Bertran
Safe limits on voltage reduction efficiency in GPUs: a direct measurement approach. MICRO 2015: 294-307 - 2014
- [c7]Liang Wang, Ramon Bertran
Characterization of transient error tolerance for a class of mobile embedded applications. IISWC 2014: 74-75 - [c6]Ramon Bertran
Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities. MICRO 2014: 368-380 - 2013
- [j5]Ramon Bertran
Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up. Comput. J. 56(2): 198-213 (2013) - [j4]Ramon Bertran, Yutaka Sugawara, Hans M. Jacobson, Alper Buyuktosunoglu, Pradip Bose:
Application-level power and performance characterization and optimization on IBM Blue Gene/Q systems. IBM J. Res. Dev. 57(1/2): 4 (2013) - [j3]Ramon Bertran
A Systematic Methodology to Generate Decomposable and Responsive Power Models for CMPs. IEEE Trans. Computers 62(7): 1289-1302 (2013) - 2012
- [j2]Ramon Bertran
Energy accounting for shared virtualized environments under DVFS using PMC-based power models. Future Gener. Comput. Syst. 28(2): 457-468 (2012) - [c5]Ramon Bertran
Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks. MICRO 2012: 199-211 - [c4]Ramon Bertran
POTRA: a framework for building power models for next generation multicore architectures. SIGMETRICS 2012: 427-428 - 2011
- [j1]Ramon Bertran
Local Memory Design Space Exploration for High-Performance Computing. Comput. J. 54(5): 786-799 (2011) - [c3]Lluc Alvarez
Design space exploration for aggressive core replication schemes in CMPs. HPDC 2011: 269-270 - 2010
- [c2]Ramon Bertran, Yolanda Becerra
Accurate energy accounting for shared virtualized environments using PMC-based power modeling techniques. GRID 2010: 1-8 - [c1]Ramon Bertran
Decomposable and responsive power models for multicore processors using performance counters. ICS 2010: 147-158
Coauthor Index
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last updated on 2024-08-05 20:24 CEST by the dblp team
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